EDS1216AABH, EDS1216CABH
Write Cycle
tCK
tCH tCL
CLK
tRC
VIH
CKE
tRP
tRAS
tRCD
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
/CS
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
/RAS
tSI tHI
/CAS
/WE
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
BS
tSI tHI
tSI tHI
tSI tHI
A10
tSI tHI
tSI tHI
Address
tSI
tHI
UDQM
LDQM
tSI tHI tSI tHI tSI tHI tSI tHI
DQ (input)
tDPL
DQ (output)
Bank 0
Precharge
Bank 0
Write
CL = 2
BL = 4
Bank 0
Active
Bank 0 access
= VIH or VIL
Mode Register Set Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
VIH
CKE
/CS
/RAS
/CAS
/WE
BS
code
C: b’
Address
valid
C: b
R: b
UDQM
LDQM
b
b+3
b’ b’+1 b’+2 b’+3
DQ (output)
DQ (input)
High-Z
lMRD
lRP
lRCD
Output mask
lRCD = 3
Precharge
If needed
Mode
register
Set
Bank 3
Active
Bank 3
Read
/CAS latency = 3
Burst length = 4
= VIH or VIL
Data Sheet E0410E40 (Ver. 4.0)
41
ELPIDA [ ELPIDA MEMORY ]
