欢迎访问ic37.com |
会员登录 免费注册
发布采购

EDS1216AABH-75-E 参数 Datasheet PDF下载

EDS1216AABH-75-E图片预览
型号: EDS1216AABH-75-E
PDF下载: 下载PDF文件 查看货源
内容描述: 128M位的SDRAM (8M字×16位) [128M bits SDRAM (8M words x 16 bits)]
分类和应用: 存储内存集成电路动态存储器时钟
文件页数/大小: 49 页 / 694 K
品牌: ELPIDA [ ELPIDA MEMORY ]
 浏览型号EDS1216AABH-75-E的Datasheet PDF文件第32页浏览型号EDS1216AABH-75-E的Datasheet PDF文件第33页浏览型号EDS1216AABH-75-E的Datasheet PDF文件第34页浏览型号EDS1216AABH-75-E的Datasheet PDF文件第35页浏览型号EDS1216AABH-75-E的Datasheet PDF文件第37页浏览型号EDS1216AABH-75-E的Datasheet PDF文件第38页浏览型号EDS1216AABH-75-E的Datasheet PDF文件第39页浏览型号EDS1216AABH-75-E的Datasheet PDF文件第40页  
EDS1216AABH, EDS1216CABH  
Write command to Precharge command interval (same bank)  
When the precharge command is executed for the same bank as the write command that preceded it, the minimum  
interval between the two commands is 1 clock. However, if the burst write operation is unfinished, the input data  
must be masked by means of UDQM and LDQM for assurance of the clock defined by tDPL.  
CLK  
PRE/PALL  
WRIT  
in A0  
Command  
UDQM  
LDQM  
DQ  
in A1  
in A2  
tDPL  
WRITE to PRECHARGE Command Interval (same bank) (BL = 4 (To stop write operation))  
CLK  
PRE/PALL  
Command  
WRIT  
in A0  
UDQM  
LDQM  
DQ  
in A1  
in A2  
in A3  
tDPL  
WRITE to PRECHARGE Command Interval (same bank) (BL = 4 (To write all data))  
Data Sheet E0410E40 (Ver. 4.0)  
36  
 复制成功!