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EDJ1108BABG-DG-E 参数 Datasheet PDF下载

EDJ1108BABG-DG-E图片预览
型号: EDJ1108BABG-DG-E
PDF下载: 下载PDF文件 查看货源
内容描述: 1G位DDR3 SDRAM [1G bits DDR3 SDRAM]
分类和应用: 存储内存集成电路动态存储器双倍数据速率时钟
文件页数/大小: 148 页 / 1878 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EDJ1108BABG, EDJ1116BABG  
Write Leveling Mode Exit  
The following sequence describes how the Write Leveling Mode should be exited:  
1. After the last rising strobe edge(see T111), stop driving the strobe signals (see ~T128). Note: From now on, DQ  
pins are in undefined driving mode, and will remain undefined, until tMOD after the respective MR command  
(T145).  
2. Drive ODT pin low (tIS must be satisfied) and continue registering low (see T128).  
3. After the RTT is switched off: disable Write Level Mode via MR command (see T132).  
4. After tMOD is satisfied (T145), any valid commands may be registered. (MR commands may already be issued  
after tMRD (T136).  
T111  
T112  
T116  
T117  
T128 T131  
T132  
T136  
MRS  
T145  
Valid  
CK, /CK  
Command  
WL_off  
1
tMOD  
BA  
Valid  
VVaalidlid  
tIS  
tMRD  
ODT  
tODTL_off  
RTT_DQS-/DQS  
DQS-/DQS  
RTT_DQ  
tWLO + tWLOE  
DQ  
Result = 1  
Timing Details Write leveling Exit  
Data Sheet E1248E40 (Ver. 4.0)  
86  
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