EDJ1108BABG, EDJ1116BABG
Write Leveling Procedure
Memory controller initiates Leveling mode of all DRAMs by setting bit 7 of MR1 to 1. Since the controller levelizes
rank at a time, the output of other rank must be disabled by setting MR1 bit A12 to 1. Controller may assert ODT
after tMOD, time at which DRAM is ready to accept the ODT signal.
Controller may drive DQS low and /DQS high after a delay of tWLDQSEN, at which time DRAM has applied on-die
termination on these signals. After tWLMRD, controller provides a single DQS, /DQS edge which is used by the
DRAM to sample CK driven from controller. tWLMRD timing is controller dependent.
DRAM samples CK status with rising edge of DQS and provides feedback on all the DQ bits asynchronously after
tWLO timing. There is a DQ output uncertainty of tWLOE defined to allow mismatch on DQ bits; there are no read
strobes (DQS, /DQS) needed for these DQs. Controller samples incoming DQ and decides to increment or
decrement DQS delay setting and launches the next DQS, /DQS pulse after some time, which is controller
dependent.
Once a 0 to 1 transition is detected, the controller locks DQS delay setting and write leveling is achieved for the
device. The below figure describes detailed timing diagram for overall procedure and the timing parameters are
shown in below figure.
T2
T1
tWLS
tWLS
tWLH
tWLH
NOP
5
*
CK
/CK
2
3
4
2
3
*
*
*
*
*
Command MRS
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tMOD
6
6
*
*
ODT
tDQSH (min.)
tDQSL (min.) tDQSH (min.) tDQSL (min.)
tWLDQSEN
diff_DQS*4
tWLOE
tWLO
tWLMRD
tWLO
All DQs,
Prime DQ*1
Remaining
DQs
Notes:1. DRAM has the option to drive leveling feedback on a prime DQ or all DQs. If feedback is driven only on one DQ,
the remaining DQs must be driven low as shown in above Figure, and maintained at this state through out
the leveling procedure.
2. MRS : Load MR1 to enter write leveling mode.
3. NOP : NOP or deselec
4. diff_DQS is the differential data strobe (DQS, /DQS). Timing reference points are the zero crossing. DQS is
shown with solid line, /DQS is shown with dotted line.
5. CK, /CK : CK is shown with solid dark line, where as /CK is drawn with dotted line.
6. DQS needs to fulfill minimum pulse width requirements tDQSH (min.) and tDQSL (min.) as defined for regular
writes; the max pulse width is system dependent.
Timing Details Write leveling Sequence
Data Sheet E1248E40 (Ver. 4.0)
85
ELPIDA [ ELPIDA MEMORY ]
