EDJ1108BABG, EDJ1116BABG
DDR3 SDRAM Mode Register 1 [MR1]
The Mode Register MR1 stores the data for enabling or disabling the DLL, output driver strength, RTT_Nom
impedance, additive latency, write leveling enable, TDQS enable and Qoff. The Mode Register 1 is written by
asserting low on /CS, /RAS, /CAS, /WE, high on BA0 and low on BA1, while controlling the states of address pins
according to the table below
MR1 Programming
Data Sheet E1248E40 (Ver. 4.0)
76