EDJ1108BABG, EDJ1116BABG
DDR3 SDRAM Mode Register 3 [MR3]
The Mode Register MR3 controls Multi Purpose Registers (MPR). The Mode Register 3 is written by asserting low
on /CS, /RAS, /CAS, /WE, high on BA1 and BA0, while controlling the states of address pins according to the table
below.
Address field
BA2 BA1 BA0 A13 A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Mode register 3
0*1
0*1
1
1
MPR MPR Loc
MPR Address
A1 A0
MPR location
2
MPR Operation
A2
0
0
1
1
0
1
0
1
Predefined pattern*
MPR
RFU
RFU
RFU
3
Normal operation
*
0
1
Data flow from MPR
N
otes : 1. BA2,A3 toA13 are reserved for future use (RFU) and must be programmed to 0 during MRS.
2. The predefined pattern will be used for read synchronization.
3 . When MPR control is set for normal operation, MR3 A[2]=0, MR3 A[1:0] will be ignored.
MR3 Programming
Data Sheet E1248E40 (Ver. 4.0)
78
ELPIDA [ ELPIDA MEMORY ]
