EDJ1108BABG, EDJ1116BABG
RESET and Initialization Procedure
Power-Up and Initialization Sequence
1. Apply power (/RESET is recommended to be maintained below 0.2 × VDD, (all other inputs may be undefined). )
/RESET needs to be maintained for minimum 200µs with stable power. CKE is pulled low anytime before
/RESET being de-asserted (min. time 10ns). The power voltage ramp time between 300mV to VDD (min.) must
be no greater than 200ms; and during the ramp, VDD > VDDQ and (VDD − VDDQ) < 0.3V.
• VDD and VDDQ are driven from a single power converter output
AND
• The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD
on one side and must be larger than or equal to VSSQ and VSS on the other side. In addition, VTT is limited to
0.95V max once power ramp is finished,
AND
• VREF tracks VDDQ/2.
OR
• Apply VDD without any slope reversal before or at the same time as VDDQ.
• Apply VDDQ without any slope reversal before or at the same time as VTT and VREF.
• The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD
on one side and must be larger than or equal to VSSQ and VSS on the other side.
2. After /RESET is de-asserted, wait for another 500µs until CKE become active. During this time, the DRAM will
start internal state initialization; this will be done independently of external clocks.
3. Clocks (CK, /CK) need to be started and stabilized for at least 10ns or 5tCK (which is larger) before CKE goes
active. Since CKE is a synchronous signal, the corresponding set up time to clock (tIS) must be met. Also a NOP
or DESL command must be registered (with tIS set up time to clock) before CKE goes active. Once the CKE
registered “high” after Reset, CKE needs to be continuously registered high until the initialization sequence is
finished, including expiration of tDLLK and tZQinit.
4. The DDR3 SDRAM will keep its on-die termination in high-impedance state during /RESET being asserted at
least until CKE being registered high. Therefore, the ODT signal may be in undefined state until tIS before CKE
being registered high. After that, the ODT signal must be kept inactive (low) until the power-up and initialization
sequence is finished, including expiration of tDLLK and tZQinit.
5. After CKE being registered high, wait minimum of tXPR, before issuing the first MRS command to load mode
register. (tXPR = max. (tXS ; 5 × tCK)
6. Issue MRS command to load MR2 with all application settings. (To issue MRS command for MR2, provide low to
BA0 and BA2, high to BA1.)
7. Issue MRS command to load MR3 with all application settings. (To issue MRS command for MR3, provide low to
BA2, high to BA0 and BA1.)
8. Issue MRS command to load MR1 with all application settings and DLL enabled. (To issue DLL Enable
command, provide low to A0, high to BA0 and low to BA1 and BA2).
9. Issue MRS command to load MR0 with all application settings and DLL reset. (To issue DLL reset command,
provide high to A8 and low to BA0 to BA2).
10.Issue ZQCL command to start ZQ calibration.
11.Wait for both tDLLK and tZQinit completed.
12.The DDR3 SDRAM is now ready for normal operation.
Data Sheet E1248E40 (Ver. 4.0)
72
ELPIDA [ ELPIDA MEMORY ]
