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EDJ1108BABG-AC-E 参数 Datasheet PDF下载

EDJ1108BABG-AC-E图片预览
型号: EDJ1108BABG-AC-E
PDF下载: 下载PDF文件 查看货源
内容描述: 1G位DDR3 SDRAM [1G bits DDR3 SDRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 148 页 / 1878 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EDJ1108BABG, EDJ1116BABG  
Programming the Mode Register  
For application flexibility, various functions, features and modes are programmable in four mode registers, provided  
by the DDR3 SDRAM, as user defined variables, and they must be programmed via a Mode Register Set (MRS)  
command. As the default values of the Mode Registers (MR#) are not defined, content of mode registers must be  
fully initialized and/or re-initialized, i.e. written, after Power-up and/or reset for proper operation. Also the contents of  
the mode registers can be altered by re-executing the MRS command during normal operation. When programming  
the mode registers, even if the user chooses to modify only a sub-set of the MRS fields, all address fields within the  
accessed mode register must be redefined when the MRS command is issued. MRS command and DLL Reset  
does not affect array contents, which means these commands can be executed any time after power-up without  
affecting the array contents.  
The mode register set command cycle time, tMRD is required to complete the write operation to the mode register  
and is the minimum time required between two MRS commands. The MRS command to non-MRS command delay,  
tMOD, is required for the DRAM to update the features except DLL reset and is the minimum time required from an  
MRS command to a non-MRS command excluding NOP and DESL. The mode register contents can be changed  
using the same command and timing requirements during normal operation as long as the DRAM is in idle state, i.e.  
all banks are in the precharged state with tRP satisfied, all data bursts are completed and CKE is already high prior  
to writing into the mode register. The mode registers are divided into various fields depending on the functionality  
and/or modes.  
Mode Register Set Command Cycle Time (tMRD)  
tMRD is the minimum time required from an MRS command to the next MRS command. As DLL enable and DLL  
reset are both MRS commands, tMRD is applicable between MRS to MR1 for DLL enable and MRS to MR0 for DLL  
reset, and not tMOD.  
/CK  
CK  
Command  
MRS  
NOP  
MRS  
NOP  
tMRD  
tMRD Timing  
MRS Command to Non-MRS Command Delay (tMOD)  
tMOD is the minimum time required from an MRS command to a non-MRS command excluding NOP and DESL.  
Note that additional restrictions may apply, for example, MRS to MR0 for DLL reset followed by read.  
/CK  
CK  
Command  
MRS  
NOP  
non-MRS  
NOP  
tMOD  
Old  
setting  
Updating  
New Setting  
tMOD Timing  
Data Sheet E1248E40 (Ver. 4.0)  
74  
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