EDJ1108BABG, EDJ1116BABG
Clock Jitter [DDR3-1600, 1333]
-GL, -GN
1600
-DG, -DJ
1333
Data rate (Mbps)
Parameter
Symbol
min.
max.
3333
min.
max.
3333
Unit
ps
Notes
1
Average clock period
tCK (avg)
1250
1500
tCK(avg)min + tCK(avg)max+ tCK(avg)min + tCK(avg)max+
Absolute clock period
Clock period jitter
Clock period jitter during
DLL locking period
Cycle to cycle period Jitter
Cycle to cycle clock period jitter
during DLL locking period
tCK (abs)
tJIT (per)
ps
ps
ps
ps
ps
2
6
6
7
7
tJIT(per)min
tJIT(per)max tJIT(per)min
tJIT(per)max
80
−70
70
−80
tJIT (per, lck) −60
tJIT (cc)
60
−70
70
140
120
160
140
tJIT (cc, lck)
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across 6 cycles
Cumulative error across 7 cycles
Cumulative error across 8 cycles
Cumulative error across 9 cycles
tERR (2per)
tERR (3per)
tERR (4per)
tERR (5per)
tERR (6per)
tERR (7per)
tERR (8per)
tERR (9per)
−103
103
122
136
147
155
163
169
175
180
184
188
−118
−140
−155
−168
−177
−186
−193
−200
−205
−210
−215
118
140
155
168
177
186
193
200
205
210
215
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
8
8
8
8
8
8
8
8
8
8
8
−122
−136
−147
−155
−163
−169
−175
Cumulative error across 10 cycles tERR (10per) −180
Cumulative error across 11 cycles tERR (11per) −184
Cumulative error across 12 cycles tERR (12per) −188
Cumulative error across
n = 13, 14…49, 50 cycles
tERR (nper) min. = (1+0.68in(n)) x tJIT(per) min
tERR (nper) max. = (1+0.68in(n)) x tJIT(per) max
tERR (nper)
tCH (avg)
tCL (avg)
tCH (abs)
ps
9
tCK
(avg)
tCK
(avg)
tCK
(avg)
tCK
(avg)
Average high pulse width
0.47
0.47
0.43
0.43
0.53
0.47
0.47
0.43
0.43
0.53
3
Average low pulse width
0.53
0.53
4
Absolute clock high pulse width
10, 11
Absolute clock low pulse width
Duty cycle jitter
tCL (abs)
tJIT (duty)
10, 12
5
ps
Data Sheet E1248E40 (Ver. 4.0)
60
ELPIDA [ ELPIDA MEMORY ]
