EDJ1104BBSE, EDJ1108BBSE, EDJ1116BBSE
AC Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V, VSS, VSSQ = 0V)
• New units tCK(avg) and nCK, are introduced in DDR3.
tCK(avg): actual tCK(avg) of the input clock under operation.
nCK: one clock cycle of the input clock, counting the actual clock edges.
AC Characteristics [DDR3-1600, 1333]
-GL, -GN
-DG, -DJ
1333
Data rate (Mbps)
Parameter
1600
min.
Symbol
max.
3333
min.
max.
3333
Unit
ps
Notes
6
Average clock cycle time
Minimum clock cycle time
(DLL-off mode)
tCK (avg)
1250
1500
tCK (DLL-off)
8
8
ns
Average CK high-level width
tCH (avg)
tCL (avg)
0.47
0.47
0.53
0.53
0.47
0.47
0.53
0.53
tCK (avg)
tCK (avg)
Average CK low-level width
Active to read or write
command delay
12.5 (GL)
12 (DG)
tRCD
tRP
ns
ns
ns
ns
26
26
26
26
13.75 (GN)
13.5 (DJ)
12.5 (GL)
13.75 (GN)
47.5 (GL)
48.75 (GN)
12 (DG)
13.5 (DJ)
48 (DG)
49.5 (DJ)
Precharge command period
Active to active/auto-refresh
command time
tRC
9 ×
tREFI
9 ×
tREFI
Active to precharge command
tRAS
35
36
Active bank A to active bank B
command period
(x4)
Active bank A to active bank B
command period
(x8)
Active bank A to active bank B
command period
(x16)
tRRD
tRRD
tRRD
tRRD
tRRD
tRRD
6
6
ns
26, 27
26, 27
26, 27
26, 27
26, 27
26, 27
4
4
nCK
ns
6
6
4
4
nCK
ns
7.5
4
7.5
4
nCK
Four active window
(x4)
tFAW
30
30
ns
26
(x8)
tFAW
tFAW
30
40
30
45
ns
ns
26
26
(x16)
Address and control input hold
time
tIH (base)
tIS (base)
120
140
ps
ps
ps
16, 23
16, 23
(VIH/VIL (DC) levels)
Address and control input
setup time
45
65
(VIH/VIL (AC) levels)
Address and control input
tIS (base)
AC150
16, 23,
31
setup time
45 + 125
65 + 125
(VIH/VIL (AC150) levels)
DQ and DM input hold time
tDH (base)
tDS (base)
tIPW
45
65
ps
ps
ps
ps
ps
ps
ps
17, 25
17, 25
32
(VIH/VIL (DC) levels)
DQ and DM input setup time
(VIH/VIL (AC) levels)
Control and Address input pulse
width for each input
DQ and DM input pulse width for
each input
10
30
560
360
620
400
tDIPW
32
12, 13,
14, 37
12, 13,
14, 37
12, 13,
14, 37
DQ high-impedance time
tHZ (DQ)
tLZ (DQ)
tHZ (DQS)
225
225
225
250
250
250
DQ low-impedance time
−450
−500
DQS, /DQS high-impedance time
(RL + BL/2 reference)
Data Sheet E1375E50 (Ver. 5.0)
52
ELPIDA [ ELPIDA MEMORY ]
