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EDJ1116BBSE-8A-F 参数 Datasheet PDF下载

EDJ1116BBSE-8A-F图片预览
型号: EDJ1116BBSE-8A-F
PDF下载: 下载PDF文件 查看货源
内容描述: 1G位DDR3 SDRAM [1G bits DDR3 SDRAM]
分类和应用: 存储内存集成电路动态存储器双倍数据速率
文件页数/大小: 151 页 / 1895 K
品牌: ELPIDA [ ELPIDA MEMORY ]
 浏览型号EDJ1116BBSE-8A-F的Datasheet PDF文件第46页浏览型号EDJ1116BBSE-8A-F的Datasheet PDF文件第47页浏览型号EDJ1116BBSE-8A-F的Datasheet PDF文件第48页浏览型号EDJ1116BBSE-8A-F的Datasheet PDF文件第49页浏览型号EDJ1116BBSE-8A-F的Datasheet PDF文件第51页浏览型号EDJ1116BBSE-8A-F的Datasheet PDF文件第52页浏览型号EDJ1116BBSE-8A-F的Datasheet PDF文件第53页浏览型号EDJ1116BBSE-8A-F的Datasheet PDF文件第54页  
EDJ1104BBSE, EDJ1108BBSE, EDJ1116BBSE  
[DDR3-1066 Speed Bins]  
Speed Bin  
DDR3-1066F  
7-7-7  
DDR3-1066G  
8-8-8  
CL-tRCD-tRP  
/CAS write  
Symbol  
latency  
min.  
max.  
20  
min.  
max.  
20  
Unit  
ns  
Notes  
tAA  
13.125  
13.125  
13.125  
50.625  
37.5  
15  
tRCD  
15  
ns  
tRP  
15  
ns  
tRC  
52.50  
37.5  
ns  
tRAS  
9 × tREFI  
Reserved  
Reserved  
3.3  
9 × tREFI  
Reserved  
Reserved  
3.3  
ns  
9
tCK (avg)@CL=5  
CWL = 5  
CWL = 6  
CWL = 5  
CWL = 6  
CWL = 5  
CWL = 6  
CWL = 5  
CWL = 6  
Reserved  
Reserved  
2.5  
Reserved  
Reserved  
2.5  
ns  
1, 2, 3, 4, 6  
ns  
4
tCK (avg)@CL=6  
tCK (avg)@CL=7  
tCK (avg)@CL=8  
ns  
1, 2, 3, 6  
1, 2, 3, 4  
4
Reserved  
Reserved  
1.875  
Reserved  
Reserved  
< 2.5  
Reserved  
Reserved  
Reserved  
Reserved  
1.875  
6, 8  
Reserved  
Reserved  
Reserved  
Reserved  
< 2.5  
ns  
ns  
ns  
1, 2, 3, 4  
4
Reserved  
1.875  
Reserved  
< 2.5  
ns  
ns  
1, 2, 3  
Supported CL settings  
Supported CWL settings  
6, 7, 8  
5, 6  
nCK  
nCK  
5, 6  
[DDR3-800 Speed Bins]  
Speed Bin  
DDR3-800F  
5-5-5  
DDR3-800E  
6-6-6  
CL-tRCD-tRP  
/CAS write  
latency  
Symbol  
min.  
12.5  
12.5  
12.5  
50  
max.  
20  
min.  
15  
max.  
20  
Unit  
ns  
Notes  
tAA  
tRCD  
15  
ns  
tRP  
15  
ns  
tRC  
52.5  
37.5  
Reserved  
2.5  
ns  
tRAS  
37.5  
2.5  
9 × tREFI  
3.3  
9 × tREFI  
Reserved  
3.3  
ns  
9
tCK (avg)@CL=5  
tCK (avg)@CL=6  
Supported CL settings  
CWL = 5  
CWL = 5  
ns  
1, 2, 3, 4  
1, 2, 3  
2.5  
3.3  
ns  
5, 6  
6
nCK  
Supported CWL  
settings  
5
5
nCK  
Notes: 1 The CL setting and CWL setting result in tCK (avg) (min.) and tCK (avg) (max.) requirements. When  
making a selection of tCK (avg), both need to be fulfilled: Requirements from CL setting as well as  
requirements from CWL setting.  
2. tCK (avg) (min.) limits: Since /CAS latency is not purely analog - data and strobe output are synchronized  
by the DLL - all possible intermediate frequencies may not be guaranteed. An application should use the  
next smaller JEDEC standard tCK (avg) value (2.5, 1.875, 1.5, or 1.25ns) when calculating  
CL (nCK) = tAA (ns) / tCK (avg)(ns), rounding up to the next ‘Supported CL’.  
3. tCK (avg) (max.) limits: Calculate tCK (avg) + tAA (max.)/CL selected and round the resulting tCK (avg)  
down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875ns or 1.25ns). This result is tCK (avg) (max.)  
corresponding to CL selected.  
Data Sheet E1375E50 (Ver. 5.0)  
50  
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