EDJ1104BBSE, EDJ1108BBSE, EDJ1116BBSE
Parameter
Symbol
IDD3N
Description
CKE: H; External clock: on; tCK, CL: see Table Timings used for IDD and IDDQ
Measurement-Loop Patterns table; BL: 8*1; AL: 0; /CS: stable at 1;
Command, Address, Bank Address Inputs: partially toggling according to IDD2N
and IDD3N Measurement-Loop Pattern; data I/O: FLOATING; DM: stable at 0;
bank activity: all banks open; output buffer and RTT: enabled in MR*2;
ODT signal: stable at 0; pattern details: see IDD2N and IDD3N
Measurement-Loop Pattern table
Active standby current
CKE: L; External clock: on; tCK, CL: see Table Timings used for IDD and IDDQ
Measurement-Loop Patterns table; BL: 8*1; AL: 0; /CS: stable at 1;
Command, Address, bank address inputs: stable at 0; data I/O: FLOATING;
DM:stable at 0; bank activity: all banks open; output buffer and RTT:
enabled in MR*2; ODT signal: stable at 0
Active power-down
current
IDD3P
IDD4R
CKE: H; External clock: on; tCK, CL: see Timings used for IDD and IDDQ
Measurement-Loop Patterns table; BL: 8*1, 7; AL: 0; /CS: H between
READ; Command, Address, Bank Address Inputs: partially toggling according to
IDD4R and IDDQ4R Measurement-Loop Pattern table; data I/O: seamless read
data burst with different data between one burst and the next one according to
IDD4R and IDDQ4R Measurement-Loop Pattern table; DM: stable at 0;
bank activity: all banks open, READ commands cycling through banks:
0,0,1,1,2,2,... (see IDD4R and IDDQ4R Measurement-Loop Pattern table); output
buffer and
Operating burstr
current
RTT: enabled in MR*2; ODT signal: stable at 0; pattern details: see IDD4R and
IDDQ4R Measurement-Loop Pattern table
Operating burst read
IDDQ current
Same definitI/on like for IDD4R, however measuring IDDQ current instead of IDD
IDDQ4R
IDD4W
current
CKE: H; External clock: on; tCK, CL: see Timings used for IDD and IDDQ
Measurement-Loop Patterns table; BL: 8*1; AL: 0; /CS: H between WR; command,
address, bank address inputs: partially toggling according to IDD4W
Measurement-Loop Pattern table; data I/O: seamless write data burst with
different data between one burst and the next one according to IDD4W
Measurement-Loop Pattern table; DM: stable at 0; bank activity: all banks open,
WR commands cycling through banks: 0,0,1,1,2,2,... (see IDD4W Measurement-
Loop Pattern table); output buffer and RTT: enabled in MR*2; ODT signal: stable
at H; pattern details: see IDD4W Measurement-Loop Pattern table
Operating burst write
current
CKE: H; External clock: on; tCK, CL, nRFC: see Timings used for IDD and IDDQ
Measurement-Loop Patterns table; BL: 8*1; AL: 0; /CS: H between REF;
Command, Address, Bank Address Inputs: partially toggling according to IDD5B
Measurement-Loop Pattern table; data I/O: FLOATING; DM: stable at 0;
bank activity: REF command every nRFC (IDD5B Measurement-Loop Pattern);
output buffer and RTT: enabled in MR*2; ODT signal: stable at 0; pattern
details: see IDD5B Measurement-Loop Pattern table
Burst refresh current
IDD5B
IDD6
TC: 0 to 85°C; ASR: disabled*4; SRT:
Normal*5; CKE: L; External clock: off; CK and /CK: L; CL: see Timings used for
IDD and IDDQ Measurement-Loop Patterns table; BL: 8*1;
AL: 0; /CS, command, address, bank address, data I/O: FLOATING; DM: stable
at 0; bank activity: Self-Refresh operatI/On; output buffer and RTT: enabled in
MR*2; ODT signal: FLOATING
Self refresh current:
normal temperature
range
Data Sheet E1375E50 (Ver. 5.0)
36
ELPIDA [ ELPIDA MEMORY ]
