EDJ1104BBSE, EDJ1108BBSE, EDJ1116BBSE
Basic IDD and IDDQ Measurement Conditions
Parameter
Symbol
Description
CKE: H; External clock: on; tCK, nRC, nRAS, CL: see Timings used for IDD and
IDDQ Measurement-Loop Patterns table; BL: 8*1; AL: 0; /CS: H between ACT and
PRE; Command, Address, Bank Address Inputs: partially toggling according to
IDD0 Measurement-loop pattern table; Data I/O: FLOATING; DM: stable at 0;
Bank activity: cycling with one bank active at a time: 0,0,1,1,2,2,... (see IDD0
Measurement-Loop Pattern table); output buffer and RTT: enabled in MR*2; ODT
signal: stable at 0; pattern details: see IDD0 Measurement-Loop Pattern table
Operating one bank
active precharge
current
IDD0
CKE: H; external clock: On; tCK, nRC, nRAS, nRCD, CL: see Timings used for IDD
and IDDQ Measurement-Loop Patterns table; BL: 8(1,7); AL: 0; /CS: H between
ACT, READ and PRE; Command, Address, Bank Address Inputs, data I/O: partially
toggling according to IDD1 Measurement-Loop Pattern table;
DM: stable at 0; bank activity: cycling with one bank active at a time: 0,0,1,1,2,2,...
(see IDD1 Measurement-Loop Pattern table); Output buffer and RTT: enabled in
MR*2; ODT Signal: stable at 0; Pattern details: see IDD1 Measurement-Loop
Pattern table
Operating one bank
active-read-precharge
current
IDD1
CKE: H; External clock: on; tCK, CL: see Timings used for IDD and IDDQ
Measurement-Loop patterns table BL: 8*1; AL: 0; /CS: stable at 1;
Command, Address, Bank address Inputs: partially toggling according to IDD2N
and IDD3N Measurement-Loop Pattern table; data I/O: FLOATING; DM: stable at 0;
bank activity: all banks closed; output buffer and RTT: enabled in mode registers*2;
ODT signal: stable at 0; pattern details: see IDD2N and IDD3N Measurement-Loop
Pattern table
Precharge standby
current
IDD2N
CKE: H; External clock: on; tCK, CL: see Timings used for IDD and IDDQ
Measurement-Loop Patterns table; BL: 8*1; AL: 0; /CS: stable at 1;
Precharge standby
ODT current
Command, Address, Bank Address Inputs: partially toggling according to IDD2NT
and IDDQ2NT Measurement-Loop Pattern table; data I/O: FLOATING; DM: stable
at 0; bank activity: all banks closed; output buffer and RTT: enabled in MR*2; ODT
signal: toggling according to IDD2NT and IDDQ2NT Measurement-Loop pattern
table; pattern details: see IDD2NT and IDDQ2NT Measurement-Loop Pattern table
IDD2NT
Precharge standby
ODT IDDQ current
Same definition like for IDD2NT, however measuring IDDQ current instead of IDD
IDDQ2NT
IDD2P0
current
CKE: L; External clock: on; tCK, CL: see Timings used for IDD and IDDQ
Measurement-Loop Patterns table; BL: 8*1; AL: 0; /CS: stable at 1;
Command, Address, bank Address inputs: stable at 0; data I/O: FLOATING; DM:
stable at 0; bank activity: all banks closed; output buffer and RTT: EMR *2; ODT
signal: stable at 0; pecharge power down mode: slow exit*3
Precharge power-down
current slow exit
CKE: L; External clock: on; tCK, CL: see Timings used for IDD and IDDQ
Measurement-Loop Patterns table; BL: 8*1; AL: 0; /CS: stable at 1;
Precharge power-down
current fast exit
IDD2P1
IDD2Q
Command, Address, Bank Address Inputs: stable at 0; data I/O: FLOATING;
DM:stable at 0; bank activity: all banks closed; output buffer and RTT: enabled in
MR*2; ODT signal: stable at 0; pecharge power down mode: fast exit*3
CKE: H; External clock: On; tCK, CL: see Timings used for IDD and IDDQ
Measurement-Loop Patterns table; BL: 8*1; AL: 0; /CS: stable at 1;
Command, Address, Bank Address Inputs: stable at 0; data I/O: FLOATING;
DM: stable at 0;bank activity: all banks closed; output buffer and RTT: enabled in
MR*2; ODT signal: stable at 0
Precharge quiet
standby current
Data Sheet E1375E50 (Ver. 5.0)
35
ELPIDA [ ELPIDA MEMORY ]
