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EDJ1116BBSE-8A-F 参数 Datasheet PDF下载

EDJ1116BBSE-8A-F图片预览
型号: EDJ1116BBSE-8A-F
PDF下载: 下载PDF文件 查看货源
内容描述: 1G位DDR3 SDRAM [1G bits DDR3 SDRAM]
分类和应用: 存储内存集成电路动态存储器双倍数据速率
文件页数/大小: 151 页 / 1895 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EDJ1104BBSE, EDJ1108BBSE, EDJ1116BBSE  
Parameter  
Symbol  
Description  
TC: 0 to 95°C; ASR: Disabled*4; SRT: Extended*5; CKE: L; External clock: off; CK and  
/CK: L; CL: see Timings used for IDD and IDDQ Measurement-Loop Patterns table;  
BL: 8*1; AL: 0; /CS, command, address, bank address, data I/O: FLOATING;  
DM: stable at 0; bank activity:  
Self refresh current:  
extended temperature IDD6ET  
range  
Extended temperature self-refresh operation; output buffer and RTT: enabled in MR*2;  
ODT signal: FLOATING  
TC: 0 to 95°C; ASR: Enabled*4; SRT: Normal*5; CKE: L; External clock: off;  
CK and /CK: L; CL: see Table Timings used for IDD and IDDQ Measurement-Loop  
Patterns table; BL: 8*1; AL: 0; /CS, command, address, bank address, data I/O:  
FLOATING; DM: stable at 0; bank activity: Auto self-refresh operation; output buffer  
and RTT: enabled in MR*2; ODT signal: FLOATNG  
Auto Self-Refresh  
IDD6TC  
Current (optional)  
CKE: H; External clock: on; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see Timings  
used for IDD and IDDQ Measurement-Loop Patterns table;  
BL: 8*1; AL: CL-1; /CS: H between ACT and READA; command, address, bank address  
Inputs: partially toggling according to IDD7 Measurement-Loop Pattern table; data I/O:  
read data bursts with different data between one burst and the next one according to  
IDD7 Measurement-Loop Pattern table; DM: stable at 0; bank activity: two times  
interleaved cycling through banks (0, 1, ...7) with different addressing, see IDD7  
Measurement-Loop Pattern table; output buffer and RTT: enabled in MR*2;  
ODT signal: stable at 0; pattern details: see IDD7 Measurement-Loop Pattern table  
Operating Bank  
Interleave Read  
Current  
IDD7  
Notes: 1. Burst Length: BL8 fixed by MRS: MR0 bits [1,0] = [0,0].  
2. MR: mode register  
Output buffer enable: set MR1 bit A12 = 1 and MR1 bits [5, 1] = [0,1];  
RTT_Nom enable: set MR1 bits [9, 6, 2] = [0, 1, 1]; RTT_WR enable: set MR2 bits [10, 9] = [1,0].  
3. Precharge power down mode: set MR0 bit A12= 0 for Slow Exit or MR0 bit A12 = 1 for fast exit.  
4. Auto self refresh (ASR): set MR2 bit A6 = 0 to disable or 1 to enable feature.  
5. Self refresh temperature range (SRT): set MR0 bit A7= 0 for normal or 1 for extended temperature range.  
6. Read burst type: nibble sequential, set MR0 bit A3 = 0.  
Data Sheet E1375E50 (Ver. 5.0)  
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