EDE5104AGSE, EDE5108AGSE
T0
T1
T2
T3
T4
T5
T6
T7
T9
/CK
CK
Posted
WRIT
NOP
PRE
Command
Completion of
the Burst Write
<tDQSS
=
DQS, /DQS
DQ
>tWR
WL = RL −1 = 4
=
in0
in1
in2
in3
Burst Write Operation (RL = 5, WL = 4, BL = 4 tWR = 3 (AL=2, CL=3))
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
/CK
CK
Write to Read = CL - 1 + BL/2 + tWTR (2) = 6
NOP
Posted
READ
NOP
Command
DQS, /DQS
DQ
AL = 2
CL = 3
WL = RL –1 = 4
RL = 5
>tWTR
=
in0
in1
in2
in3
out0 out1
Burst Write Followed by Burst Read (RL = 5, BL = 4, WL = 4, tWTR = 2 (AL=2, CL=3))
The minimum number of clock from the burst write command to the burst read command is CL - 1 + BL/2 + a write
to-read-turn-around-time (tWTR). This tWTR is not a write recovery time (tWR) but the time required to transfer the
4bit write data from the input buffer into sense amplifiers in the array.
T0
T1
T2
T3
T4
T5
T6
T7
T8
/CK
CK
Posted
WRIT
Posted
WRIT
Command
NOP
NOP
A
B
DQS, /DQS
WL = RL − 1 = 4
in
in
in
in
in
in
in
in
DQ
A0 A1 A2 A3 B0 B1 B2 B3
Seamless Burst Write Operation (RL = 5, WL = 4, BL = 4)
Enabling a write command every other clock supports the seamless burst write operation. This operation is allowed
regardless of same or different banks as long as the banks are activated.
Preliminary Data Sheet E0715E20 (Ver. 2.0)
44
ELPIDA [ ELPIDA MEMORY ]
