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EDE5104AGSE-5C-E 参数 Datasheet PDF下载

EDE5104AGSE-5C-E图片预览
型号: EDE5104AGSE-5C-E
PDF下载: 下载PDF文件 查看货源
内容描述: 512M位DDR2 SDRAM [512M bits DDR2 SDRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 65 页 / 657 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EDE5104AGSE, EDE5108AGSE  
Precharge Command [PRE]  
The precharge command is used to precharge or close a bank that has been activated. The precharge command is  
triggered when /CS, /RAS and /WE are low and /CAS is high at the rising edge of the clock. The precharge  
command can be used to precharge each bank independently or all banks simultaneously. Three address bits A10,  
BA0 and BA1 are used to define which bank to precharge when the command is issued.  
[Bank Selection for Precharge by Address Bits]  
A10  
L
BA0  
L
BA1  
L
Precharged Bank(s)  
Bank 0 only  
L
H
L
Bank 1 only  
L
L
H
Bank 2 only  
L
H
H
Bank 3 only  
H
×
×
All banks 0 to 3  
Remark: H: VIH, L: VIL, ×: VIH or VIL  
Burst Read Operation Followed by Precharge  
Minimum read to precharge command spacing to the same bank = AL + BL/2 clocks  
For the earliest possible precharge, the precharge command may be issued on the rising edge that is  
“Additive latency (AL) + BL/2 clocks” after a Read command. A new bank active (command) may be issued to the  
same bank after the RAS precharge time (tRP). A precharge command cannot be issued until tRAS is satisfied.  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
/CK  
CK  
Posted  
READ  
NOP  
AL + 2 clocks  
PRE  
NOP  
ACT  
NOP  
Command  
DQS, /DQS  
> t  
RP  
=
AL = 1  
CL = 3  
RL = 4  
out0 out1 out2 out3  
CL = 3  
DQ  
> t  
RAS  
=
Burst Read Operation Followed by Precharge (RL = 4, BL = 4 (AL=1, CL=3))  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
/CK  
CK  
Posted  
READ  
ACT  
NOP  
AL + 2 clocks  
PRE  
NOP  
NOP  
Command  
DQS, /DQS  
> t  
RP  
=
AL = 2  
CL = 3  
RL = 5  
out0 out1 out2 out3  
CL = 3  
DQ  
> t  
RAS  
=
Burst Read Operation Followed by Precharge (RL = 5, BL = 4 (AL=2, CL=3))  
Preliminary Data Sheet E0715E20 (Ver. 2.0)  
47  
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