EDE5104AGSE, EDE5108AGSE
Bank Activate Command [ACT]
The bank activate command is issued by holding /CAS and /WE high with /CS and /RAS low at the rising edge of the
clock. The bank addresses BA0 and BA1, are used to select the desired bank. The row address A0 through A13 is
used to determine which row to activate in the selected bank. The Bank activate command must be applied before
any read or write operation can be executed. Immediately after the bank active command, the DDR2 SDRAM can
accept a read or write command on the following clock cycle. If a R/W command is issued to a bank that has not
satisfied the tRCD (min.) specification, then additive latency must be programmed into the device to delay when the
R/W command is internally issued to the device. The additive latency value must be chosen to assure tRCD (min.)
is satisfied. Additive latencies of 0, 1, 2, 3 and 4 are supported. Once a bank has been activated it must be
precharged before another bank activate command can be applied to the same bank. The bank active and
precharge times are defined as tRAS and tRP, respectively. The minimum time interval between successive bank
activate commands to the same bank is determined by the /RAS cycle time of the device (tRC), which is equal to
tRAS + tRP. The minimum time interval between successive bank activate commands to the different bank is
determined by (tRRD).
T0
T1
T2
T3
Tn
Tn+1
Tn+2
PRE
Tn+3
/CK
CK
Posted
READ
Posted
READ
Command
ACT
ACT
PRE
ACT
tRCD(min.)
Address
ROW: 0
COL: 0
ROW: 1
tCCD
COL: 1
ROW: 0
Bank0 Read begins
Additive latency (AL)
tRCD =1
tRRD
tRAS
tRP
tRC
Bank0
Active
Bank1
Active
Bank0
Precharge
Bank1
Precharge Active
Bank0
Bank Activate Command Cycle (tRCD = 3, AL = 2, tRP = 3, tRRD = 2, tCCD = 2)
Preliminary Data Sheet E0715E20 (Ver. 2.0)
37
ELPIDA [ ELPIDA MEMORY ]
