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EDE1108AFBG-8G-F 参数 Datasheet PDF下载

EDE1108AFBG-8G-F图片预览
型号: EDE1108AFBG-8G-F
PDF下载: 下载PDF文件 查看货源
内容描述: 1G位DDR2 SDRAM [1G bits DDR2 SDRAM]
分类和应用: 存储内存集成电路动态存储器双倍数据速率
文件页数/大小: 78 页 / 734 K
品牌: ELPIDA [ ELPIDA MEMORY ]
 浏览型号EDE1108AFBG-8G-F的Datasheet PDF文件第16页浏览型号EDE1108AFBG-8G-F的Datasheet PDF文件第17页浏览型号EDE1108AFBG-8G-F的Datasheet PDF文件第18页浏览型号EDE1108AFBG-8G-F的Datasheet PDF文件第19页浏览型号EDE1108AFBG-8G-F的Datasheet PDF文件第21页浏览型号EDE1108AFBG-8G-F的Datasheet PDF文件第22页浏览型号EDE1108AFBG-8G-F的Datasheet PDF文件第23页浏览型号EDE1108AFBG-8G-F的Datasheet PDF文件第24页  
EDE1108AFBG  
Clock Jitter  
-8E, -8G  
800  
-6E  
Frequency (Mbps)  
Parameter  
667  
Symbol  
min.  
max.  
8000  
100  
min.  
3000  
125  
max.  
8000  
125  
Unit  
ps  
Notes  
Average clock period  
Clock period jitter  
tCK (avg)  
tJIT (per)  
2500  
100  
1
5
ps  
Clock period jitter during  
DLL locking period  
tJIT  
(per, lck)  
80  
80  
100  
100  
250  
200  
ps  
ps  
ps  
5
6
6
Cycle to cycle period jitter  
tJIT (cc)  
200  
160  
Cycle to cycle clock period jitter  
during DLL locking period  
tJIT (cc, lck)  
Cumulative error across 2 cycles  
Cumulative error across 3 cycles  
Cumulative error across 4 cycles  
Cumulative error across 5 cycles  
tERR (2per) 150  
tERR (3per) 175  
tERR (4per) 200  
tERR (5per) 200  
150  
175  
200  
200  
175  
225  
250  
250  
175  
225  
250  
250  
ps  
ps  
ps  
ps  
7
7
7
7
Cumulative error across  
n=6,7,8,9,10 cycles  
tERR  
(6-10per)  
300  
300  
450  
350  
450  
350  
450  
ps  
ps  
7
7
Cumulative error across  
n=11, 12,…49,50 cycles  
tERR  
(11-50per)  
450  
Average high pulse width  
Average low pulse width  
Duty cycle jitter  
tCH (avg)  
tCL (avg)  
tJIT (duty)  
0.48  
0.48  
100  
0.52  
0.52  
100  
0.48  
0.48  
125  
0.52  
0.52  
125  
tCK (avg)  
tCK (avg)  
ps  
2
3
4
Notes: 1. tCK (avg) is calculated as the average clock period across any consecutive 200cycle window.  
N  
tCK(avg) =  
tCKj  
N
j =1  
N = 200  
2. tCH (avg) is defined as the average high pulse width, as calculated across any consecutive 200 high  
pulses.  
N  
tCH(avg) =  
tCHj (N ×tCK(avg))  
j =1  
N = 200  
3. tCL (avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses.  
N  
tCL(avg) =  
tCLj (N × tCK(avg))  
j =1  
N = 200  
4. tJIT (duty) is defined as the cumulative set of tCH jitter and tCL jitter. tCH jitter is the largest deviation of  
any single tCH from tCH (avg). tCL jitter is the largest deviation of any single tCL from tCL (avg).  
tJIT (duty) is not subject to production test.  
tJIT (duty) = Min./Max. of {tJIT (CH), tJIT (CL)}, where:  
tJIT (CH) = {tCHj- tCH (avg) where j = 1 to 200}  
tJIT (CL) = {tCLj tCL (avg) where j = 1 to 200}  
5. tJIT (per) is defined as the largest deviation of any single tCK from tCK (avg).  
tJIT (per) = Min./Max. of { tCKj tCK (avg) where j = 1 to 200}  
tJIT (per) defines the single period jitter when the DLL is already locked. tJIT (per, lck) uses the same  
definition for single period jitter, during the DLL locking period only. tJIT (per) and tJIT (per, lck) are not  
subject to production test.  
Preliminary Data Sheet E1430E20 (Ver. 2.0)  
20  
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