EDE1104ACSE, EDE1108ACSE, EDE1116ACSE
ODT AC Electrical Characteristics
Parameter
Symbol
tAOND
min.
2
max.
2
Unit
tCK
Notes
ODT turn-on delay
ODT turn-on
-8E, -6E
tAON
tAC (min)
tAC (max) + 700
ps
1, 3
1
-5C
tAON
tAC (min)
tAC (max) + 1000
ps
ODT turn-on (power down mode)
ODT turn-off delay
tAONPD
tAOFD
tAOF
tAC(min) + 2000
2tCK + tAC(max) + 1000
ps
2.5
2.5
tCK
ps
5, 6
ODT turn-off
tAC(min)
tAC(max) + 600
2, 4, 5, 6
ODT turn-off (power down mode)
ODT to power down entry latency
ODT power down exit latency
tAOFPD
tANPD
tAXPD
tAC(min) + 2000
2.5tCK + tAC(max) + 1000
ps
3
8
3
8
tCK
tCK
Notes: 1. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.
ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND.
2. ODT turn off time min is when the device starts to turn off ODT resistance.
ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.
3. When the device is operated with input clock jitter, this parameter needs to be derated by the actual
tERR(6-10per) of the input clock. (output deratings are relative to the SDRAM input clock.)
4. When the device is operated with input clock jitter, this parameter needs to be derated by
{−tJIT(duty) max. − tERR(6-10per) max. } and { −tJIT(duty) min. − tERR(6-10per) min. } of the actual input
clock.(output deratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR2-667 SDRAM has tERR(6-10per) min. = −272ps,
tERR(6-10per) max. = +293ps, tJIT(duty) min. = −106ps and tJIT(duty) max. = +94ps, then
tAOF min.(derated) = tAOF min. + { −tJIT(duty) max. − tERR(6-10per) max. } = −450ps + { −94ps − 293ps}
= −837ps and tAOF max.(derated) = tAOF max. + { −tJIT(duty) min. − tERR(6-10per) min. } = 1050ps +
{ 106ps + 272ps} = +1428ps.
5. For tAOFD of DDR2-533, the 1/2 clock of tCK in the 2.5 × tCK assumes a tCH, input clock high pulse
width of 0.5 relative to tCK. tAOF min. and tAOF max. should each be derated by the same amount as
the actual amount of tCH offset present at the DRAM input with respect to 0.5. For example, if an input
clock has a worst case tCH of 0.45, the tAOF min. should be derated by subtracting 0.05 × tCK from it,
whereas if an input clock has a worst case tCH of 0.55, the tAOF max. should be derated by adding 0.05
× tCK to it. Therefore, we have;
tAOF min.(derated) = tAC min. − [0.5 − Min.(0.5, tCH min.)] × tCK
tAOF max.(derated) = tAC max. + 0.6 + [Max.(0.5, tCH max.) − 0.5] × tCK
or
tAOF min.(derated) = Min.(tAC min., tAC min. − [0.5 − tCH min.] × tCK)
tAOF max.(derated) = 0.6 + Max.(tAC max., tAC max. + [tCH max. − 0.5] × tCK)
where tCH min. and tCH max. are the minimum and maximum of tCH actually measured at the DRAM
input balls.
6. For tAOFD of DDR2-667/800, the 1/2 clock of nCK in the 2.5 × nCK assumes a tCH(avg), average input
clock high pulse width of 0.5 relative to tCK(avg). tAOF min. and tAOF max. should each be derated by
the same amount as the actual amount of tCH(avg) offset present at the DRAM input with respect to 0.5.
For example, if an input clock has a worst case tCH(avg) of 0.48, the tAOF min. should be derated by
subtracting 0.02 × tCK(avg) from it, whereas if an input clock has a worst case tCH(avg) of 0.52,
the tAOF max. should be derated by adding 0.02 × tCK(avg) to it. Therefore, we have;
tAOF min.(derated) = tAC min. − [0.5 − Min.(0.5, tCH(avg) min.)] × tCK(avg)
tAOF max.(derated) = tAC max. + 0.6 + [Max.(0.5, tCH(avg) max.) − 0.5] × tCK(avg)
or
tAOF min.(derated) = Min.(tAC min., tAC min. − [0.5 − tCH(avg) min.] × tCK(avg))
tAOF max.(derated) = 0.6 + Max.(tAC max., tAC max. + [tCH(avg) max. − 0.5] × tCK(avg))
where tCH(avg) min. and tCH(avg) max. are the minimum and maximum of tCH(avg) actually measured
at the DRAM input balls.
Data Sheet E0975E50 (Ver.5.0)
19
ELPIDA [ ELPIDA MEMORY ]
