EDE1104ACSE, EDE1108ACSE, EDE1116ACSE
AC Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V, VSS, VSSQ = 0V) [DDR2-533]
-5C
Speed bin
DDR2-533 (4-4-4)
Parameter
Symbol
tRCD
tRP
min.
15
max.
Unit
ns
Notes
Active to read or write command delay
Precharge command period
Active to active/auto-refresh command time
DQ output access time from CK, /CK
DQS output access time from CK, /CK
CK high-level width
15
ns
tRC
60
ns
tAC
−500
−450
0.45
0.45
+500
+450
0.55
0.55
ps
tDQSCK
tCH
ps
tCK
tCK
CK low-level width
tCL
Min.
(tCL, tCH)
CK half period
tHP
tCK
ps
ps
Clock cycle time
(CL = 6)
3750
8000
(CL = 5)
(CL = 4)
(CL = 3)
tCK
tCK
tCK
3750
3750
5000
8000
8000
8000
ps
ps
ps
ps
DQ and DM input hold time
(differential strobe)
tDH (base)
225
5
4
DQ and DM input hold time
(single-ended strobe)
tDH1 (base) –25
tDS (base) 100
tDS1 (base) –25
ps
ps
ps
DQ and DM input setup time
(differential strobe)
DQ and DM input setup time
(single-ended strobe)
Control and Address input pulse width for each input
DQ and DM input pulse width for each input
Data-out high-impedance time from CK,/CK
Data-out low-impedance time from CK,/CK
DQS-DQ skew for DQS and associated DQ signals
DQ hold skew factor
tIPW
tDIPW
tHZ
0.6
tCK
tCK
ps
0.35
tAC max.
tAC max.
300
tLZ
tAC min.
ps
tDQSQ
tQHS
tQH
ps
400
ps
DQ/DQS output hold time from DQS
tHP – tQHS
−0.25
0.35
0.35
0.2
ps
DQS latching rising transitions to associated clock edges tDQSS
+0.25
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
tDQSH
tDQSL
tDSS
tDSH
0.2
tMRD
2
tWPST
tWPRE
tIH (base)
tIS (base)
tRPRE
tRPST
tRAS
0.4
0.6
Write preamble
0.35
375
Address and control input hold time
Address and control input setup time
Read preamble
5
4
250
ps
0.9
1.1
tCK
tCK
ns
Read postamble
0.4
0.6
Active to precharge command
Active to auto-precharge delay
45
70000
tRAP
tRCD min.
ns
Data Sheet E0975E50 (Ver.5.0)
16
ELPIDA [ ELPIDA MEMORY ]
