EDE1104ACSE, EDE1108ACSE, EDE1116ACSE
-5C
Speed bin
Parameter
DDR2-533 (4-4-4)
Symbol
tRRD
tRRD
tFAW
min.
7.5
max.
Unit
ns
Notes
Active bank A to active bank B command period
(EDE1104AC, EDE1108AC)
(EDE1116AC)
10
ns
Four active window period
(EDE1104AC, EDE1108AC)
37.5
ns
(EDE1116AC)
tFAW
tCCD
tWR
50
2
ns
/CAS to /CAS command delay
Write recovery time
tCK
ns
15
WR +
RU(tRP/tCK)
Auto precharge write recovery + precharge time
tDAL
tCK
1, 9
14
Internal write to read command delay
tWTR
tRTP
7.5
ns
Internal read to precharge command delay
Exit self-refresh to a non-read command
Exit self-refresh to a read command
7.5
ns
tXSNR
tXSRD
tXP
tRFC + 10
ns
200
2
tCK
tCK
tCK
Exit precharge power down to any non-read command
Exit active power down to read command
tXARD
2
3
Exit active power down to read command
(slow exit/low power mode)
tXARDS
6 − AL
tCK
2, 3
CKE minimum pulse width (high and low pulse width)
Output impedance test driver delay
tCKE
tOIT
3
tCK
ns
0
12
12
MRS command to ODT update delay
tMOD
tRFC
0
ns
Auto-refresh to active/auto-refresh command time
127.5
ns
Average periodic refresh interval
(0°C ≤ TC ≤ +85°C)
tREFI
7.8
3.9
µs
µs
ns
(+85°C < TC ≤ +95°C)
tREFI
Minimum time clocks remains ON after CKE
asynchronously drops low
tDELAY
tIS + tCK + tIH
Notes: 1. For each of the terms above, if not already an integer, round to the next higher integer.
2. AL: Additive Latency.
3. MRS A12 bit defines which active power down exit timing to be applied.
4. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the
VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under test.
5. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the
VIL(DC) level for a rising signal and VIH(DC) for a falling signal applied to the device under test.
CK
DQS
/CK
/DQS
tIS
tIH
tIS
tIH
tDS tDH
tDS tDH
VDDQ
VDDQ
VIH (AC)(min.)
VIH (DC)(min.)
VREF
VIH (AC)(min.)
VIH (DC)(min.)
VREF
VIL (DC)(max.)
VIL (AC)(max.)
VSS
VIL (DC)(max.)
VIL (AC)(max.)
VSS
Input Waveform Timing 1 (tDS, tDH)
Input Waveform Timing 2 (tIS, tIH)
Data Sheet E0975E50 (Ver.5.0)
17
ELPIDA [ ELPIDA MEMORY ]
