EDE1104ABSE, EDE1108ABSE, EDE1116ABSE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK
/CK
NOP
Command
WRIT
A
NOP
WRIT
B
DQS, /DQS
WL = 3
in in in in in in in in in in in in
A0 A1 A2 A3 B0 B1 B2 B3 B4 B5 B6 B7
DQ
Burst interrupt is only
allowed at this timing.
Write Interrupt by Write (WL = 3, BL = 8)
Notes :1. Write burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited.
2. Write burst of 8 can only be interrupted by another write command. Write burst interruption by read
command or precharge command is prohibited.
3. Write burst interrupt must occur exactly two clocks after previous write command. Any other write burst
interrupt timings are prohibited.
4. Write burst interruption is allowed to any bank inside DRAM.
5. Write burst with auto precharge enabled is not allowed to interrupt.
6. Write burst interruption is allowed by another write with auto precharge command.
7. All command timings are referenced to burst length set in the mode register. They are not referenced to
actual burst. For example, minimum write to precharge timing is WL + BL/2 + tWR where tWR starts with
the rising clock after the un-interrupted burst end and not from the end of actual burst end.
Data Sheet E0852E50 (Ver. 5.0)
60
ELPIDA [ ELPIDA MEMORY ]
