EDE1104ABSE, EDE1108ABSE, EDE1116ABSE
AC Timing for IDD Test Conditions
For purposes of IDD testing, the following parameters are to be utilized.
DDR2-800
DDR2-667
DDR2-667
DDR2-533
DDR2-400
Parameter
5-5-5
5
4-4-4
4
5-5-5
5
4-4-4
4
3-3-3
3
Unit
tCK
CL (IDD)
tRCD (IDD)
12.5
57.5
7.5
12
15
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRC (IDD)
57
60
60
55
tRRD (IDD)-×4/×8
tRRD (IDD)-×16
tFAW (IDD)-×4/×8
tFAW (IDD)-×16
tCK (IDD)
7.5
10
7.5
10
7.5
7.5
10
10
10
35
37.5
50
37.5
50
37.5
50
37.5
50
⎯
2.5
3
3
3.75
45
5
tRAS (min.)(IDD)
tRAS (max.)(IDD)
tRP (IDD)
45
45
45
40
70000
12.5
127.5
70000
12
70000
15
70000
15
70000
15
tRFC (IDD)
127.5
127.5
127.5
127.5
IDD7 Timing Patterns for 8 Banks
The detailed timings are shown in the IDD7 Timing Patterns for 8 Banks tables.
[×4/×8 organization]
Speed bins
DDR2-400
DDR2-533
DDR2-667
DDR2-800
Timing Patterns
A0 RA0 A1 RA1 A2 RA2 A3 RA3 A4 RA4 A5 RA5 A6 RA6 A7 RA7
A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D
[×16 organization]
Speed bins
DDR2-400
DDR2-533
DDR2-667
Timing Patterns
A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D
Remark: A = Active. RA = Read with auto precharge. D = Deselect
Notes: 1. All banks are being interleaved at minimum tRC (IDD) without violating tRRD (IDD) and tFAW (IDD) using
a Burst length = 4.
2. Control and address bus inputs are STABLE during DESELECTs.
3. IOUT = 0mA.
Data Sheet E0852E50 (Ver. 5.0)
10
ELPIDA [ ELPIDA MEMORY ]
