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EDE1108ABSE-4A-E 参数 Datasheet PDF下载

EDE1108ABSE-4A-E图片预览
型号: EDE1108ABSE-4A-E
PDF下载: 下载PDF文件 查看货源
内容描述: 1G位DDR2 SDRAM [1G bits DDR2 SDRAM]
分类和应用: 存储内存集成电路动态存储器双倍数据速率时钟
文件页数/大小: 82 页 / 645 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EDE1104ABSE, EDE1108ABSE, EDE1116ABSE  
max.  
× 8  
× 16  
× 4  
Parameter  
Symbol Grade  
Unit  
mA  
Test condition  
-8E  
-6C  
-6E  
-5C  
-4A  
350  
335  
335  
320  
310  
350  
335  
335  
320  
310  
335  
320  
310  
tCK = tCK (IDD);  
Refresh command at every tRFC (IDD) interval;  
CKE is H, /CS is H between valid commands;  
Other control and address bus inputs are SWITCHING;  
Data bus inputs are SWITCHING  
Auto-refresh current IDD5  
-8E  
-6C  
-6E  
-5C  
-4A  
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
10  
Self-Refresh Mode;  
CK and /CK at 0V;  
CKE 0.2V;  
Other control and address bus inputs are FLOATING;  
Data bus inputs are FLOATING  
Self-refresh current  
IDD6*7  
mA  
mA  
all bank interleaving reads, IOUT = 0mA;  
-8E  
-6C  
-6E  
-5C  
-4A  
330  
305  
305  
300  
280  
340  
315  
315  
310  
300  
360  
350  
340  
BL = 4, CL = CL(IDD), AL = tRCD (IDD) 1 × tCK (IDD);  
tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD),  
tFAW = tFAW (IDD), tRCD = 1 × tCK (IDD);  
CKE is H, CS is H between valid commands;  
Address bus inputs are STABLE during DESELECTs;  
Data pattern is same as IDD4W;  
Operating current  
(Bank interleaving)  
IDD7  
Notes: 1. IDD specifications are tested after the device is properly initialized.  
2. Input slew rate is specified by AC Input Test Condition.  
3. IDD parameters are specified with ODT disabled.  
4. Data bus consists of DQ, DM, DQS, /DQS, RDQS and /RDQS. IDD values must be met with all  
combinations of EMRS bits 10 and 11.  
5. Definitions for IDD  
L is defined as VIN VIL (AC) (max.)  
H is defined as VIN VIH (AC) (min.)  
STABLE is defined as inputs stable at an H or L level  
FLOATING is defined as inputs at VREF = VDDQ/2  
SWITCHING is defined as:  
inputs changing between H and L every other clock cycle (once per two clocks) for address and control  
signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals  
not including masks or strobes.  
6. Refer to AC Timing for IDD Test Conditions.  
7. When TC +85°C, IDD6 must be derated by 80%.  
IDD6 will increase by this amount (IDD6 will be 18mA), if TC +85°C and double refresh option is still  
enabled.  
Data Sheet E0852E50 (Ver. 5.0)  
9