EDE1104ABSE, EDE1108ABSE, EDE1116ABSE
AC Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.8V 0.1V, VSS, VSSQ = 0V) [DDR2-800, 667]
• New units tCK(avg) and nCK, are introduced in DDR2-800 and DDR2-667
tCK(avg): actual tCK(avg) of the input clock under operation.
nCK: one clock cycle of the input clock, counting the actual clock edges.
-8E
800
min.
-6C, -6E
667
Frequency (Mbps)
Parameter
Symbol
CL
max.
5
min.
max.
5
Unit
nCK
Notes
4 (-6C)
5 (-6E)
/CAS latency
5
12 (-6C)
15 (-6E)
Active to read or write command delay
Precharge command period
tRCD
tRP
12.5
12.5
⎯
⎯
⎯
⎯
⎯
⎯
ns
ns
ns
12 (-6C)
15 (-6E)
57 (-6C)
60 (-6E)
Active to active/auto-refresh command time tRC
57.5
DQ output access time from CK, /CK
DQS output access time from CK, /CK
CK high-level width
tAC
−400
+400
+350
0.52
0.52
−450
−400
0.48
0.48
+450
+400
0.52
0.52
ps
ps
10
10
tDQSCK −350
tCH (avg) 0.48
tCL(avg) 0.48
tCK (avg) 13
tCK (avg) 13
CK low-level width
Min. (tCL(abs),
tCH(abs))
Min.(tCL(abs),
tCH(abs))
CK half period
tHP
⎯
⎯
ps
6, 13
Clock cycle time
tCK (avg) 2500
tDH (base) 125
tDS (base) 50
8000
⎯
3000
175
8000
⎯
ps
ps
ps
13
5
DQ and DM input hold time
DQ and DM input setup time
⎯
100
⎯
4
Control and Address input pulse width for
each input
tIPW
0.6
⎯
0.6
⎯
⎯
tCK (avg)
tCK (avg)
DQ and DM input pulse width for each input tDIPW
0.35
⎯
0.35
Data-out high-impedance time from CK,/CK tHZ
DQS, /DQS low-impedance time from
CK,/CK
⎯
tAC max.
⎯
tAC max. ps
tAC max. ps
tAC max. ps
10
10
10
tLZ (DQS) tAC min.
tLZ (DQ) 2 × tAC min. tAC max. 2 × tAC min.
tAC max. tAC min.
DQ low-impedance time from CK,/CK
DQS-DQ skew for DQS and associated DQ
signals
tDQSQ
⎯
200
⎯
240
ps
DQ hold skew factor
tQHS
tQH
⎯
300
⎯
340
ps
ps
7
8
DQ/DQS output hold time from DQS
tHP – tQHS
⎯
tHP – tQHS
⎯
DQS latching rising transitions to associated
clock edges
tDQSS
−0.25
+0.25
−0.25
+0.25
tCK (avg)
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
tDQSH
tDQSL
tDSS
0.35
0.35
0.2
0.2
2
⎯
0.35
0.35
0.2
⎯
tCK (avg)
tCK (avg)
tCK (avg)
tCK (avg)
nCK
⎯
⎯
⎯
⎯
tDSH
⎯
0.2
⎯
tMRD
⎯
2
⎯
tWPST
tWPRE
0.4
0.35
0.6
⎯
0.4
0.6
⎯
tCK (avg)
tCK (avg)
ps
Write preamble
0.35
275
200
0.9
Address and control input hold time
Address and control input setup time
Read preamble
tIH (base) 250
tIS (base) 175
⎯
⎯
5
4
⎯
⎯
ps
tRPRE
tRPST
tRAS
0.9
1.1
0.6
70000
⎯
1.1
0.6
70000
⎯
tCK (avg) 11
Read postamble
0.4
0.4
tCK (avg) 12
Active to precharge command
Active to auto-precharge delay
45
45
ns
ns
tRAP
tRCD min.
tRCD min.
Data Sheet E0852E50 (Ver. 5.0)
14
ELPIDA [ ELPIDA MEMORY ]
