EDE1104ABSE, EDE1108ABSE, EDE1116ABSE
DC Characteristics 1 (TC = 0°C to +85°C, VDD, VDDQ = 1.8V 0.1V)
max.
× 4
× 8
× 16
Parameter
Symbol Grade
Unit
mA
Test condition
-8E
-6C
110
100
100
95
110
100
100
95
⎯
⎯
120
110
110
one bank; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Operating current
(ACT-PRE)
IDD0
IDD1
-6E
-5C
-4A
90
90
one bank; IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
-8E
-6C
-6E
-5C
-4A
120
110
110
105
100
125
115
115
110
105
⎯
⎯
140
130
130
tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
Operating current
(ACT-READ-PRE)
mA
-8E
-6C
IDD2P -6E
10
10
10
10
10
10
10
10
10
10
⎯
⎯
10
10
10
all banks idle;
tCK = tCK (IDD);
CKE is L;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
Precharge power-
down standby
current
mA
mA
mA
mA
mA
mA
-5C
-4A
-8E
-6C
IDD2Q -6E
-5C
40
35
35
30
30
40
35
35
30
30
⎯
⎯
35
30
30
all banks idle;
tCK = tCK (IDD);
CKE is H, /CS is H;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
Precharge quiet
standby current
-4A
-8E
-6C
45
40
40
35
30
45
40
40
35
30
⎯
⎯
40
35
30
all banks idle;
tCK = tCK (IDD);
CKE is H, /CS is H;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Idle standby current IDD2N -6E
-5C
-4A
-8E
-6C
IDD3P-F -6E
-5C
40
35
35
30
30
40
35
35
30
30
⎯
⎯
35
30
30
Fast PDN Exit
MRS (12) = 0
all banks open;
tCK = tCK (IDD);
CKE is L;
Other control and address
bus inputs are STABLE;
Data bus inputs are
FLOATING
-4A
Active power-down
standby current
-8E
-6C
IDD3P-S -6E
-5C
20
20
20
20
20
20
20
20
20
20
⎯
⎯
20
20
20
Slow PDN Exit
MRS (12) = 1
-4A
-8E
-6C
IDD3N -6E
-5C
90
80
80
65
55
90
80
80
65
55
⎯
⎯
80
65
55
all banks open;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Active standby
current
-4A
all banks open, continuous burst reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
-8E
-6C
IDD4R -6E
-5C
205
175
175
145
120
225
195
195
165
140
⎯
⎯
230
190
160
Operating current
(Burst read
operating)
mA
mA
-4A
Data pattern is same as IDD4W
all banks open, continuous burst writes;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
-8E
-6C
IDD4W -6E
-5C
205
175
175
145
120
225
195
195
165
140
⎯
⎯
245
200
170
Operating current
(Burst write
operating)
-4A
Data Sheet E0852E50 (Ver. 5.0)
8
ELPIDA [ ELPIDA MEMORY ]
