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EDD51323DBH-6ELS-F 参数 Datasheet PDF下载

EDD51323DBH-6ELS-F图片预览
型号: EDD51323DBH-6ELS-F
PDF下载: 下载PDF文件 查看货源
内容描述: 512M DDR位移动RAM ™ WTR (宽温度范围) ,低功耗功能 [512M bits DDR Mobile RAM™ WTR (Wide Temperature Range), Low Power Function]
分类和应用: 双倍数据速率
文件页数/大小: 60 页 / 761 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EDD51323DBH-LS  
Extended Mode Register  
The extended mode register is as follows;  
Reserved  
Driver Strength  
: A12 through A7, A4, A3  
: A6 through A5  
Partial Array Self-Refresh  
: A2 through A0  
Following extended mode register programming, no command can be issued before at least 2 clocks have elapsed.  
Driver Strength  
By setting specific parameter on A6 and A5, driving capability of data output drivers is selected.  
Auto Temperature Compensated Self-Refresh (ATCSR)  
The DDR Mobile RAM automatically changes the self-refresh cycle by on die temperature sensor. No extended  
mode register program is required. Manual TCSR (Temperature Compensated Self-Refresh) is not implemented.  
Partial Array Self-Refresh  
Memory array size to be refreshed during self-refresh operation is programmable in order to reduce power. Data  
outside the defined area will not be retained during self-refresh.  
Deep Power-Down Exit Sequence  
In order to exit from the deep power-down mode and enter into the idle mode, the following sequence is needed,  
which is similar to the power-on sequence.  
(1) A 200µs or longer pause must precede any command other than ignore command (DESL).  
(2) After the pause, all banks must be precharged using the precharge command (the precharge all banks command  
is convenient).  
(3) Once the precharge is completed and the minimum tRP is satisfied, two or more Auto-refresh must be performed.  
(4) Both the mode register and the extended mode register must be programmed. After the mode register set cycle  
or the extended mode register set cycle, tMRD (2 clocks minimum) pause must be satisfied.  
Remarks:  
1
The sequence of Auto-refresh, mode register programming and extended mode register programming above may  
be transposed.  
2
CKE must be held high.  
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0  
PASR  
1
0
0
0
0
0
0
0
DS  
0
0
Refresh Array  
All banks  
A6 A5 Driver Strength  
A2 A1 A0  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
0
1
Normal  
1/2 strength  
1/4 strength  
1/8 strength  
Bank0 & Bank1 (BA1 = 0)  
Bank0 (BA = BA1 = 0)  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Extended Mode Register Set  
Preliminary Data Sheet E1432E20 (Ver. 2.0)  
24  
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