EDD51323DBH-LS
t0
t0.5
t1
t1.5
t2
t2.5
t3
t3.5
t4
t4.5
t5
t5.5
CK
/CK
READ
NOP
Command
tRPRE
tRPST
VTT
VTT
DQS
DQ
tAC,tDQSCK
out0 out1 out2 out3
Read Operation (/CAS Latency)
Write Operation
The burst length (BL) and the burst type (BT) of the mode register are referred when a write command is issued.
The burst length (BL) determines the length of a sequential data input by the write command that can be set to 2, 4,8
or 16. The latency from write command to data input is fixed to 1. The starting address of the burst write is defined
by the column address, the bank select address (See “Pin Function”) in the cycle when the write command is issued.
DQS should be input as the strobe for the input-data and DM as well during burst operation. tWPRE prior to the first
rising edge of DQS, DQS must be set to low. tWPST after the last falling edge of DQS, the DQS pins can be
changed to high-Z. The leading low period of DQS is referred as write preamble. The last low period of DQS is
referred as write postamble.
CK
/CK
tRCD
Command
Address
NOP
ACT
Row
NOP
WRIT
NOP
Column
tWPRE
in0 in1
BL = 2
tWPST
in0 in1 in2 in3
DQS
DQ
BL = 4
BL = 8
in0 in1 in2 in3 in4 in5 in6 in7
in
in
in0 in1 in2 in3 in4 in5 in6 in7
14 15
BL = 16
BL: Burst length
Write Operation
Preliminary Data Sheet E1432E20 (Ver. 2.0)
28
ELPIDA [ ELPIDA MEMORY ]
