EDD51323DBH-LS
Operation of the DDR Mobile RAM
Initialization
The DDR Mobile RAM is initialized in the power-on sequence according to the following.
1. Provide power, the device core power (VDD) and the device I/O power (VDDQ) must be brought up
simultaneously to prevent device latch-up. Although not required, it is recommended that VDD and VDDQ are
from the same power source. Also assert and hold Clock Enable (CKE) to a LV-CMOS logic high level.
2. Once the system has established consistent device power and CKE is driven high, it is safe to apply stable clock.
3. There must be at least 200µs of valid clocks before any command may be given to the DRAM. During this time
NOP or deselect (DESL) commands must be issued on the command bus.
4. Issue a precharge all command.
5. Provide NOPs or DESL commands for at least tRP time.
6. Issue an auto-refresh command followed by NOPs or DESL command for at least tRFC time. Issue the second
auto-refresh command followed by NOPs or DESL command for at least tRFC time. Note as part of the
initialization sequence there must be two auto-refresh commands issued. The typical flow is to issue them at
Step 6, but they may also be issued between steps 10 and 11.
7. Using the MRS command, load the base mode register. Set the desired operating modes.
8. Provide NOPs or DESL commands for at least tMRD time.
9. Using the MRS command, program the extended mode register for the desired operating modes.
10.Provide NOP or DESL commands for at least tMRD time.
11.The DRAM has been properly initialized and is ready for any valid command.
Preliminary Data Sheet E1432E20 (Ver. 2.0)
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ELPIDA [ ELPIDA MEMORY ]
