EDD51323DBH-LS
Mode Register and Extended Mode Register Set
There are two mode registers, the mode register and the extended mode register so as to define the operating
mode. Parameters are set to both through the A0 to the A12 and BA0 and BA1 pins by the mode register set
command [MRS] or the extended mode register set command [EMRS]. The mode register and the extended mode
register are set by inputting signal via the A0 to the A12 and BA0 and BA1 pins during mode register set cycles.
BA0 and BA1 determine which one of the mode register or the extended mode register are set. Prior to a read or a
write operation, the mode register must be set.
Mode Register
The mode register has four fields;
Reserved
/CAS latency
Burst type
: A12 through A7
: A6 through A4
: A3
Burst length
: A2 through A0
Following mode register programming, no command can be issued before at least 2 clocks have elapsed.
/CAS Latency
/CAS latency must be set to 3.
Burst Length
Burst Length is the number of words that will be output or input in a read or write cycle. After a read burst is
completed, the output bus will become high-Z. The burst length is programmable as 2, 4, 8 and 16.
Burst Type (Burst Sequence)
The burst type specifies the order in which the burst data will be addressed. This order is programmable as either
“Sequential” or “Interleave”. “Burst Operation” shows the addressing sequence for each burst length for each burst
type.
BA0 BA1 A12 A11 A10 A9 A8 A7 A6 A5 A4
A3
BT
A2 A1
BL
A0
0
0
0
0
0
0
0
0
LMODE
MRS
A6 A5 A4 CAS Latency
A3 Burst Type
Burst Length
BT = 0 BT = 1
Reserved Reserved
A2 A1 A0
0
0
0
Reserved
0
1
Sequential
Interleave
0
0
0
1
1
0
Reserved
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
4
2
4
0
1
1
0
1
0
3
Reserved
8
8
1
1
1
0
1
1
1
0
1
Reserved
Reserved
16
16
Reserved Reserved
Reserved Reserved
Reserved Reserved
Reserved
Mode Register Set
Preliminary Data Sheet E1432E20 (Ver. 2.0)
23
ELPIDA [ ELPIDA MEMORY ]
