EDD2516AKTA-E
A Write command to the consecutive Read command interval: To interrupt the write operation
Destination row of the consecutive read
command
Bank
Row address State
address
Operation
DM must be input 1 cycle prior to the read command input to prevent from being
written invalid data. In case, the read command is input in the next cycle of the
write command, DM is not necessary.
1. Same
2. Same
3. Different
Same
Different
Any
ACTIVE
—
—*1
DM must be input 1 cycle prior to the read command input to prevent from being
written invalid data. In case, the read command is input in the next cycle of the
write command, DM is not necessary.
ACTIVE
IDLE
—*1
Note: 1. Precharge must be preceded to read command. Therefore read command can not interrupt the write
operation in this case.
WRITE to READ Command Interval (Same bank, same ROW address)
t0
t1
t2
t3
t4
t5
t6
t7
t8
CK
/CK
Command
WRIT
READ
NOP
1 cycle
CL=2
DM
High-Z
High-Z
DQ
out0 out1 out2 out3
in0 in1
in2
DQS
BL = 4
CL= 2
Data masked
[WRITE to READ delay = 1 clock cycle]
Data Sheet E0502E30 (Ver. 3.0)
33
ELPIDA [ ELPIDA MEMORY ]
