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EDD2516AKTA-6B-E 参数 Datasheet PDF下载

EDD2516AKTA-6B-E图片预览
型号: EDD2516AKTA-6B-E
PDF下载: 下载PDF文件 查看货源
内容描述: 256M比特DDR SDRAM ( 16M字×16位) [256M bits DDR SDRAM (16M words x 16 bits)]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 49 页 / 546 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EDD2516AKTA-E  
A Write command to the consecutive Read command interval: To complete the burst operation  
Destination row of the consecutive read  
command  
Bank  
Row address State  
address  
Operation  
To complete the burst operation, the consecutive read command should be  
performed tWRD (= BL/ 2 + 2) after the write command.  
Precharge the bank tWPD after the preceding write command. tRP after the  
precharge command, issue the ACT command. tRCD after the ACT command, the  
consecutive read command can be issued. See ‘A read command to the  
consecutive precharge interval’ section.  
To complete a burst operation, the consecutive read command should be  
performed tWRD (= BL/ 2 + 2) after the write command.  
Precharge the bank independently of the preceding write operation. tRP after the  
precharge command, issue the ACT command. tRCD after the ACT command, the  
consecutive read command can be issued.  
1. Same  
2. Same  
3. Different  
Same  
Different  
Any  
ACTIVE  
ACTIVE  
IDLE  
t0  
t1  
t2  
t3  
t4  
t5  
t6  
CK  
/CK  
Command  
WRIT  
NOP  
READ  
NOP  
tWRD (min)  
tWTR*  
BL/2 + 2 cycle  
DM  
out2  
DQ  
out0 out1  
in0  
in1  
in2  
in3  
DQS  
INPUT  
OUTPUT  
BL = 4  
CL = 2  
Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR.  
WRITE to READ Command Interval  
Data Sheet E0502E30 (Ver. 3.0)  
32  
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