EBE41AE4ABHA
AC Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V, VSS, VSSQ = 0V)
(DDR2 SDRAM Component Specification)
• New units tCK(avg) and nCK, are introduced in DDR2-800 and DDR2-667
tCK(avg): actual tCK(avg) of the input clock under operation.
nCK: one clock cycle of the input clock, counting the actual clock edges.
-6E
Frequency (Mbps)
667
Parameter
Symbol
CL
min.
5
max.
5
Unit
Notes
/CAS latency
nCK
Active to read or write command delay
Precharge command period
Active to active/auto-refresh command time
DQ output access time from CK, /CK
DQS output access time from CK, /CK
CK high-level width
tRCD
tRP
15
ns
15
ns
tRC
60
ns
tAC
−450
−400
0.48
0.48
+450
+400
0.52
0.52
ps
10
10
13
13
tDQSCK
tCH (avg)
tCL(avg)
ps
tCK (avg)
tCK (avg)
CK low-level width
Min.(tCL(abs),
tCH(abs))
CK half period
tHP
ps
6, 13
Clock cycle time
tCK (avg)
tDH (base)
tDS (base)
tIPW
3000
175
100
0.6
8000
ps
13
5
DQ and DM input hold time
ps
DQ and DM input setup time
ps
4
Control and Address input pulse width for each input
DQ and DM input pulse width for each input
Data-out high-impedance time from CK,/CK
DQS, /DQS low-impedance time from CK,/CK
DQ low-impedance time from CK,/CK
DQS-DQ skew for DQS and associated DQ signals
DQ hold skew factor
tCK (avg)
tCK (avg)
ps
tDIPW
0.35
tHZ
tAC max.
tAC max.
tAC max.
240
10
10
10
tLZ (DQS)
tLZ (DQ)
tDQSQ
tQHS
tAC min.
ps
2 × tAC min.
ps
ps
340
ps
7
8
DQ/DQS output hold time from DQS
tQH
tHP – tQHS
−0.25
0.35
0.35
0.2
ps
DQS latching rising transitions to associated clock edges tDQSS
+0.25
tCK (avg)
tCK (avg)
tCK (avg)
tCK (avg)
tCK (avg)
nCK
DQS input high pulse width
DQS input low pulse width
tDQSH
tDQSL
tDSS
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
tDSH
0.2
tMRD
2
tWPST
tWPRE
tIH (base)
tIS (base)
tRPRE
tRPST
tRAS
0.4
0.6
tCK (avg)
tCK (avg)
ps
Write preamble
0.35
275
Address and control input hold time
Address and control input setup time
Read preamble
5
200
ps
4
0.9
1.1
tCK (avg)
tCK (avg)
ns
11
12
Read postamble
0.4
0.6
Active to precharge command
Active to auto-precharge delay
Active bank A to active bank B command period
45
70000
tRAP
tRCD min.
7.5
ns
tRRD
ns
Data Sheet E0901E20 (Ver. 2.0)
16
ELPIDA [ ELPIDA MEMORY ]
