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EBE41AE4ABHA 参数 Datasheet PDF下载

EBE41AE4ABHA图片预览
型号: EBE41AE4ABHA
PDF下载: 下载PDF文件 查看货源
内容描述: 注册4GB DDR2 SDRAM DIMM [4GB Registered DDR2 SDRAM DIMM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 27 页 / 228 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EBE41AE4ABHA  
DC Characteristics 1 (TC = 0°C to +85°C, VDD = 1.8V ± 0.1V, VSS = 0V)  
Parameter  
Symbol Grade  
max  
Unit  
Test condition  
one bank; tCK = tCK (IDD), tRC = tRC (IDD),  
tRAS = tRAS min.(IDD);  
CKE is H, /CS is H between valid commands;  
Address bus inputs are SWITCHING;  
Data bus inputs are SWITCHING  
Operating current  
(ACT-PRE)  
IDD0  
4000  
mA  
one bank; IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0;  
tCK = tCK (IDD), tRC = tRC (IDD),  
Operating current  
(ACT-READ-PRE)  
tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);  
CKE is H, /CS is H between valid commands;  
Address bus inputs are SWITCHING;  
IDD1  
4250  
1050  
mA  
mA  
Data pattern is same as IDD4W  
all banks idle;  
tCK = tCK (IDD);  
CKE is L;  
Other control and address bus inputs are STABLE;  
Data bus inputs are FLOATING  
Precharge power-down  
standby current  
IDD2P  
all banks idle;  
tCK = tCK (IDD);  
CKE is H, /CS is H;  
Other control and address bus inputs are STABLE;  
Data bus inputs are FLOATING  
Precharge quiet standby  
current  
IDD2Q  
IDD2N  
1950  
2150  
mA  
mA  
all banks idle;  
tCK = tCK (IDD);  
CKE is H, /CS is H;  
Idle standby current  
Other control and address bus inputs are SWITCHING;  
Data bus inputs are SWITCHING  
all banks open;  
Fast PDN Exit  
IDD3P-F  
IDD3P-S  
1950  
1450  
mA  
mA  
tCK = tCK (IDD);  
MRS(12) = 0  
CKE is L;  
Active power-down  
standby current  
Other control and address  
bus inputs are STABLE;  
Data bus inputs are  
FLOATING  
Slow PDN Exit  
MRS(12) = 1  
all banks open;  
tCK = tCK (IDD), tRAS = tRAS max.(IDD),  
tRP = tRP (IDD);  
CKE is H, /CS is H between valid commands;  
Other control and address bus inputs are SWITCHING;  
Data bus inputs are SWITCHING  
Active standby current  
IDD3N  
IDD4R  
3650  
5450  
mA  
mA  
all banks open, continuous burst reads, IOUT = 0mA;  
BL = 4, CL = CL(IDD), AL = 0;  
tCK = tCK (IDD), tRAS = tRAS max.(IDD),  
tRP = tRP (IDD);  
CKE is H, /CS is H between valid commands;  
Address bus inputs are SWITCHING;  
Data pattern is same as IDD4W  
Operating current  
(Burst read operating)  
all banks open, continuous burst writes;  
BL = 4, CL = CL(IDD), AL = 0;  
tCK = tCK (IDD), tRAS = tRAS max.(IDD),  
tRP = tRP (IDD);  
CKE is H, /CS is H between valid commands;  
Address bus inputs are SWITCHING;  
Data bus inputs are SWITCHING  
Operating current  
IDD4W  
5450  
mA  
(Burst write operating)  
Data Sheet E0901E20 (Ver. 2.0)  
12  
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