EBE11UD8AGSA
AC Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V, VSS = 0V)
(DDR2 SDRAM Component Specification)
-6E
667
min.
5
-5C
533
min.
4
Frequency (Mbps)
Parameter
Symbol
CL
max.
5
max.
5
Unit
tCK
ns
Notes
/CAS latency
Active to read or write command delay
Precharge command period
tRCD
tRP
15
15
15
15
ns
Active to active/auto refresh command time tRC
60
60
ns
DQ output access time from CK, /CK
DQS output access time from CK, /CK
CK high-level width
tAC
−450
−400
0.45
0.45
+450
+400
0.55
0.55
−500
−450
0.45
0.45
+500
+450
0.55
0.55
ps
tDQSCK
tCH
ps
tCK
tCK
CK low-level width
tCL
min.
(tCL, tCH)
min.
(tCL, tCH)
CK half period
tHP
ps
Clock cycle time
tCK
tDH
tDS
3000
175
8000
3750
225
8000
ps
ps
ps
DQ and DM input hold time
DQ and DM input setup time
5
4
100
100
Control and Address input pulse width for
each input
tIPW
0.6
0.6
tCK
DQ and DM input pulse width for each input tDIPW
Data-out high-impedance time from CK,/CK tHZ
Data-out low-impedance time from CK,/CK tLZ
0.35
0.35
tCK
ps
tAC max.
tAC max.
tAC max.
tAC max.
tAC min.
tAC min.
ps
DQS-DQ skew for DQS and associated DQ
signals
tDQSQ
240
340
300
400
ps
DQ hold skew factor
tQHS
tQH
ps
ps
DQ/DQS output hold time from DQS
tHP – tQHS
tHP – tQHS
Write command to first DQS latching
transition
tDQSS
WL − 0.25
WL + 0.25
WL − 0.25
WL + 0.25 tCK
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
tDQSH
tDQSL
tDSS
tDSH
tMRD
tWPST
tWPRE
tIH
0.35
0.35
0.2
0.35
0.35
0.2
tCK
tCK
tCK
tCK
tCK
0.2
0.2
2
2
0.4
0.6
0.4
0.6
tCK
tCK
ps
Write preamble
0.35
275
200
0.9
0.35
375
250
0.9
Address and control input hold time
Address and control input setup time
Read preamble
5
4
tIS
ps
tRPRE
tRPST
tRAS
tRAP
1.1
1.1
tCK
tCK
ns
Read postamble
0.4
0.6
0.4
0.6
Active to precharge command
Active to auto-precharge delay
45
70000
45
70000
tRCD min.
tRCD min.
ns
Active bank A to active bank B command
period
tRRD
tWR
7.5
7.5
ns
Write recovery time
15
15
ns
Auto precharge write recovery + precharge
time
(tWR/tCK)+
(tRP/tCK)
(tWR/tCK)+
(tRP/tCK)
tDAL
tCK
1
Data Sheet E0827E10 (Ver. 1.0)
15
ELPIDA [ ELPIDA MEMORY ]
