EBE11UD8AEFA-6
Pin Capacitance (TA = 25°C, VDD = 1.8V ± 0.1V)
(DDR2 SDRAM Component Specification)
Parameter
Symbol Pins
min.
1.0
max.
2.0
Unit
pF
Notes
1
CLK input pin capacitance
CCK
CK, /CK
/RAS, /CAS,
/WE, /CS,
Input pin capacitance
CIN
1.0
2.5
2.0
3.5
pF
pF
1
2
CKE, ODT,
Address
DQ, DQS, /DQS,
RDQS, /RDQS, DM
Input/output pin capacitance
CI/O
Notes: 1. Matching within 0.25pF.
2. Matching within 0.50pF.
AC Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V, VSS = 0V)
(DDR2 SDRAM Component Specification)
-6E
Frequency (Mbps)
667
min.
5
Parameter
Symbol
CL
max.
5
Unit
tCK
ns
Notes
/CAS latency
Active to read or write command delay
Precharge command period
Active to active/auto refresh command time
DQ output access time from CK, /CK
DQS output access time from CK, /CK
CK high-level width
tRCD
tRP
15
15
ns
tRC
60
ns
tAC
−450
+450
+400
0.55
0.55
ps
tDQSCK −400
ps
tCH
tCL
0.45
0.45
tCK
tCK
CK low-level width
min.
(tCL, tCH)
CK half period
tHP
ps
Clock cycle time
tCK
tDH
tDS
3000
175
100
0.6
8000
ps
DQ and DM input hold time
DQ and DM input setup time
ps
5
4
ps
Control and Address input pulse width for each input tIPW
tCK
tCK
ps
DQ and DM input pulse width for each input
Data-out high-impedance time from CK,/CK
Data-out low-impedance time from CK,/CK
tDIPW
tHZ
0.35
tAC max.
tAC max.
240
tLZ
tAC min.
ps
DQS-DQ skew for DQS and associated DQ signals tDQSQ
ps
DQ hold skew factor
tQHS
tQH
340
ps
DQ/DQS output hold time from DQS
Write command to first DQS latching transition
DQS input high pulse width
tHP – tQHS
ps
tDQSS
tDQSH
tDQSL
tDSS
WL − 0.25
0.35
0.35
0.2
WL + 0.25
tCK
tCK
tCK
tCK
tCK
tCK
tCK
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
tDSH
0.2
tMRD
tWPST
2
0.4
0.6
Data Sheet E0721E10 (Ver. 1.0)
15
ELPIDA [ ELPIDA MEMORY ]
