EBE11UD8AEFA-6
DC Characteristics 1 (TC = 0°C to +85°C, VDD = 1.8V ± 0.1V, VSS = 0V)
Parameter
Symbol Grade
IDD0
max.
1000
Unit
mA
Test condition
Operating current
(ACT-PRE)
(Another rank is in IDD2P)
one bank; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Operating current
(ACT-PRE)
(Another rank is in IDD3N)
IDD0
IDD1
1480
1120
mA
mA
one bank; IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
Operating current
(ACT-READ-PRE)
tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
(Another rank is in IDD2P)
Operating current
IDD1
1600
160
mA
mA
(ACT-READ-PRE)
(Another rank is in IDD3N)
all banks idle;
tCK = tCK (IDD);
CKE is L;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
Precharge power-down
standby current
IDD2P
all banks idle;
tCK = tCK (IDD);
CKE is H, /CS is H;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
Precharge quiet standby
current
IDD2Q
IDD2N
400
560
mA
mA
all banks idle;
tCK = tCK (IDD);
CKE is H, /CS is H;
Idle standby current
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
all banks open;
Fast PDN Exit
tCK = tCK (IDD);
MRS(12) = 0
CKE is L;
IDD3P-F
IDD3P-S
640
400
mA
mA
Active power-down
standby current
Other control and address bus
inputs are STABLE;
Slow PDN Exit
MRS(12) = 1
Data bus inputs are FLOATING
all banks open;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Active standby current
IDD3N
1120
mA
Operating current
all banks open, continuous burst reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
IDD4R
IDD4R
IDD4W
IDD4W
1920
2400
1840
2320
mA
mA
mA
mA
(Burst read operating)
(Another rank is in IDD2P)
Operating current
(Burst read operating)
(Another rank is in IDD3N)
Data pattern is same as IDD4W
Operating current
all banks open, continuous burst writes;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
(Burst write operating)
(Another rank is in IDD2P)
Operating current
(Burst write operating)
(Another rank is in IDD3N)
tCK = tCK (IDD);
Auto-refresh current
(Another rank is in IDD2P)
IDD5
IDD5
2240
2720
mA
mA
Refresh command at every tRFC (IDD) interval;
CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Auto-refresh current
(Another rank is in IDD3N)
Data Sheet E0721E10 (Ver. 1.0)
11
ELPIDA [ ELPIDA MEMORY ]
