EBE11UD8AEFA-6
Parameter
Symbol Grade
IDD6
max.
96
Unit
mA
Test condition
Self Refresh Mode;
CK and /CK at 0V;
CKE ≤ 0.2V;
Self-refresh current
Other control and address bus inputs are FLOATING;
Data bus inputs are FLOATING
all bank interleaving reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = tRCD (IDD) −1 × tCK (IDD);
tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD(IDD),
tRCD = 1 × tCK (IDD);
CKE is H, CS is H between valid commands;
Address bus inputs are STABLE during DESELECTs;
Data pattern is same as IDD4W;
Operating current
IDD7
IDD7
2640
3120
mA
mA
(Bank interleaving)
(Another rank is in IDD2P)
Operating current
(Bank interleaving)
(Another rank is in IDD3N)
Notes: 1. IDD specifications are tested after the device is properly initialized.
2. Input slew rate is specified by AC Input Test Condition.
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, /DQS, RDQS, /RDQS, LDQS, /LDQS, UDQS, and /UDQS. IDD
values must be met with all combinations of EMRS bits 10 and 11.
5. Definitions for IDD
L is defined as VIN ≤ VIL (AC) (max.)
H is defined as VIN ≥ VIH (AC) (min.)
STABLE is defined as inputs stable at an H or L level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
inputs changing between H and L every other clock cycle (once per two clocks) for address and control
signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals
not including masks or strobes.
6. Refer to AC Timing for IDD Test Conditions.
AC Timing for IDD Test Conditions
For purposes of IDD testing, the following parameters are to be utilized.
DDR2-667
Parameter
5-5-5
5
Unit
tCK
ns
CL (IDD)
tRCD (IDD)
tRC (IDD)
15
60
ns
tRRD (IDD)
tCK (IDD)
7.5
3
ns
ns
tRAS (min.)(IDD)
tRAS (max.)(IDD)
tRP (IDD)
45
ns
70000
15
ns
ns
tRFC (IDD)
105
ns
Data Sheet E0721E10 (Ver. 1.0)
12
ELPIDA [ ELPIDA MEMORY ]
