EBE11UD8AEFA-6
-6E
Frequency (Mbps)
667
min.
0.35
275
200
0.9
Parameter
Symbol
tWPRE
tIH
max.
Unit
tCK
ps
Notes
Write preamble
Address and control input hold time
Address and control input setup time
Read preamble
5
4
tIS
ps
tRPRE
tRPST
tRAS
tRAP
tRRD
tWR
1.1
tCK
tCK
ns
Read postamble
0.4
0.6
Active to precharge command
Active to auto-precharge delay
Active bank A to active bank B command period
Write recovery time
45
70000
tRCD min.
7.5
ns
ns
15
ns
(tWR/tCK)+
(tRP/tCK)
Auto precharge write recovery + precharge time
tDAL
tCK
1
Internal write to read command delay
Internal read to precharge command delay
Exit self refresh to a non-read command
Exit self refresh to a read command
tWTR
tRTP
7.5
ns
7.5
ns
tXSNR
tXSRD
tRFC + 10
200
ns
tCK
Exit precharge power down to any non-read
command
tXP
2
tCK
tCK
tCK
Exit active power down to read command
tXARD
tXARDS
2
3
Exit active power down to read command
(slow exit/low power mode)
7− AL
2, 3
CKE minimum pulse width (high and low pulse width) tCKE
3
tCK
ns
Output impedance test driver delay
tOIT
0
12
Auto refresh to active/auto refresh command time
tRFC
105
ns
Average periodic refresh interval
(0°C ≤ TC ≤ +85°C)
tREFI
7.8
3.9
µs
µs
ns
(+85°C < TC ≤ +95°C)
tREFI
Minimum time clocks remains ON after CKE
asynchronously drops low
tDELAY
tIS + tCK + tIH
Notes: 1. For each of the terms above, if not already an integer, round to the next higher integer.
2. AL: Additive Latency.
3. MRS A12 bit defines which active power down exit timing to be applied.
4. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the
VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under test.
5. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the
VIH(DC) level for a rising signal and VIL(DC) for a falling signal applied to the device under test.
CK
DQS
/CK
/DQS
tIS
tIH
tIS
tIH
tDS tDH
tDS tDH
VDDQ
VDDQ
VIH (AC)(min.)
VIH (DC)(min.)
VREF
VIH (AC)(min.)
VIH (DC)(min.)
VREF
VIL (DC)(max.)
VIL (AC)(max.)
VSS
VIL (DC)(max.)
VIL (AC)(max.)
VSS
Input Waveform Timing 1 (tDS, tDH)
Input Waveform Timing 2 (tIS, tIH)
Data Sheet E0721E10 (Ver. 1.0)
16
ELPIDA [ ELPIDA MEMORY ]
