EBD25UC8AAFA
Parameter
Symbol
tRRD
min.
15
15
35
1
max
—
Unit
ns
Notes
Active to active command period
Write recovery time
tWR
—
ns
Auto precharge write recovery and precharge time
Internal write to Read command delay
Exit self refresh to non-read command
Exit self refresh to read command
Exit power down to any non-read command
Exit precharge power down to read command
Average periodic refresh interval
tDAL
—
ns
tWTR
tXSNR
tXSRD
tXPNR
tXPRD
tREF
—
tCK
ns
75
200
1
tCK
tCK
tCK
µs
1
5
4
—
7.8
Notes: 1 tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These
parameters are not referenced to a specific voltage level, but specify when the device output is no longer
driving (HZ), or begins driving (LZ).
2. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for
this parameter, but system performance (bus turnaround) will degrade accordingly.
3. The specific requirement is that DQS be valid (High, Low, or at some point on a valid transition) on or
before this CK edge. A valid transition is defined as monotonic, and meeting the input slew rate
specifications of the device. When no writes were previously in progress on the bus, DQS will be
transitioning from High-Z to logic Low. If a previous write was in progress, DQS could be High, Low, or
transitioning from High to Low at this time, depending on tDQSS.
4. A maximum of eight auto refresh commands can be posted to any given DDR SDRAM device.
5. tXPRD should be 200 tCK in the condition of the unstable CK operation during the power down mode.
6. For command/address and CK and /CK slew rate ≥ 1.0V/ns.
Data Sheet E0360E20 (Ver. 2.0)
12
ELPIDA [ ELPIDA MEMORY ]
