EBD25UC8AAFA
Pin Capacitance (TA = 25°C, VDD = 2.5V ± 0.2V)
Parameter
Symbol
CI1
Pins
max.
75
Unit
pF
Notes
Address, /RAS, /CAS, /WE,
/CS, CKE
CK, /CK
Input capacitance
Input capacitance
CI2
60
pF
Data and DQS input/output
capacitance
CO
DQ, DQS
10
pF
AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V)
(DDR SDRAM Componen Specification)
Parameter
Symbol
tCK
min.
10
max
15
Unit
ns
Notes
Clock cycle time
(CL = 2)
(CL = 2.5)
tCK
tCH
tCL
7.5
15
ns
CK high-level width
CK low-level width
0.45
0.55
0.55
tCK
tCK
0.45
min
CK half period
tHP
tAC
—
tCK
ns
(tCH, tCL)
DQ output access time from
CK, /CK
–0.75
0.75
DQS output access time from CK, /CK
tDQSCK
tDQSQ
tQH
–0.75
—
0.75
0.5
—
ns
DQS to DQ skew
ns
DQ/DQS output hold time from DQS
Data-out high-impedance time from CK, /CK
Data-out low-impedance time from CK, /CK
Read preamble
tHP – 0.75
–0.75
–0.75
0.9
ns
tHZ
0.75
0.75
1.1
0.6
—
ns
1
1
tLZ
ns
tRPRE
tRPST
tDS
tCK
tCK
ns
Read postamble
0.4
DQ and DM input setup time
0.5
DQ and DM input hold time
tDH
0.5
—
ns
DQ and DM input pulse width
Write preamble setup time
tDIPW
tWPRES
tWPRE
tWPST
tDQSS
tDSS
tDSH
tDQSH
tDQSL
tIS
1.75
0
—
ns
—
ns
3
2
Write preamble
0.25
0.4
—
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
Write postamble
0.6
1.25
—
Write command to first DQS latching transition
DQS falling edge to CK setup time
DQS falling edge hold time from CK
DQS input high pulse width
0.75
0.2
0.2
—
0.35
0.35
0.9
—
DQS input low pulse width
—
Address and control input setup time
Address and control input hold time
Mode register set command cycle time
Active to Precharge command period
Active to Active/Auto refresh command period
Auto refresh to Active/Auto refresh command period
Active to Read/Write delay
—
6
6
tIH
0.9
—
ns
tMRD
tRAS
tRC
15
—
ns
45
120000
—
ns
65
ns
tRFC
tRCD
tRP
75
—
ns
20
—
ns
Precharge to active command period
20
—
ns
Data Sheet E0360E20 (Ver. 2.0)
11
ELPIDA [ ELPIDA MEMORY ]
