EBD25UC8AAFA
DC Characteristics 1 (TA = 0 to +70°C, VDD = 2.5V ± 0.2V, VSS = 0V)
Parameter
Symbol
IDD0
Grade
max.
680
Unit
mA
Test condition
Notes
1, 2, 9
CKE ≥ VIH,
tRC = tRC (min.)
Operating current (ACTV-PRE)
CKE ≥ VIH, BL = 4,
Operating current
(ACTV-READ-PRE)
IDD1
800
mA
CL = 2.5,
1, 2, 5
tRC = tRC (min.)
Idle power down standby current
Floating idle
Standby current
IDD2P
IDD2F
48
mA
mA
CKE ≤ VIL
CKE ≥ VIH, /CS ≥ VIH
DQ, DQS, DM = VREF
4
240
4, 5
Active power down
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
120
mA
mA
mA
mA
mA
mA
mA
CKE ≤ VIL
3
standby current
CKE ≥ VIH, /CS ≥ VIH
tRAS = tRAS (max.)
CKE ≥ VIH, BL = 2,
CL = 2.5
CKE ≥ VIH, BL = 2,
CL = 2.5
tRFC = tRFC (min.),
Input ≤ VIL or ≥ VIH
Active standby current
360
3, 5, 6
1, 2, 5, 6
1, 2, 5, 6
Operating current
(Burst read operation)
Operating current
(Burst write operation)
1200
1120
1120
24
Auto refresh current
Input ≥ VDD – 0.2 V
Input ≤ 0.2 V
Self refresh current
IDD6
Operating current
(4 banks interleaving)
IDD7A
1880
BL = 4
5, 6, 7
Notes: 1. These IDD data are measured under condition that DQ pins are not connected.
2. One bank operation.
3. One bank active.
4. All banks idle.
5. Command/Address transition once per one cycle.
6. Data/Data mask transition twice per one cycle.
7. 4 banks active. Only one bank is running at tRC = tRC (min.)
8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general.
9. Command/Address transition once per one every two clock cycles.
DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V)
Parameter
Symbol
ILI
min.
–16
–5
max.
16
5
Unit
µA
Test condition
Notes
Input leakage current
Output leakage current
Output high current
Output low current
VDD ≥ VIN ≥ VSS
VDD ≥ VOUT ≥ VSS
VOUT = VTT + 0.84V
VOUT = VTT – 0.84V
ILO
µA
IOH
IOL
–16.8
16.8
—
mA
mA
1
1
—
Note: 1. DDR SDRAM component specification.
Data Sheet E0360E20 (Ver. 2.0)
10
ELPIDA [ ELPIDA MEMORY ]
