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GD25LQ40 参数 Datasheet PDF下载

GD25LQ40图片预览
型号: GD25LQ40
PDF下载: 下载PDF文件 查看货源
内容描述: [1.8V Uniform Sector Dual and Quad Serial Flash]
分类和应用:
文件页数/大小: 59 页 / 3629 K
品牌: ELM [ ELM ELECTRONICS ]
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GD25LQ40xIGx 1.8V Uniform Sector Dual and Quad Serial Flash  
http://www.elm-tech.com  
7.21. Release from Deep Power-Down and Read Device ID (RDI) (ABH)  
The Release from Power-Down and Read Device ID is a multi-purpose command. It can be used to release the  
device from the Power-Down state or obtain the devices electronic identification (ID) number.  
To release the device from the Power-Down state, the command is issued by driving the CS# pin low, shifting  
the instruction code “ABH” and driving CS# high as shown in Figure22. Release from Power-Down will take  
the time duration of tRES1 (See AC Characteristics) before the device will resume normal operation and other  
command are accepted. The CS# pin must remain high during the tRES1 time duration.  
When used only to obtain the Device ID while not in the Power-Down state, the command is initiated by  
driving the CS# pin low and shifting the instruction code “ABH” followed by 3-dummy byte. The Device ID  
bits are then shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure23.  
The Device ID value for the GD25LQ40 is listed in Manufacturer and Device Identification table. The Device  
ID can be read continuously. The command is completed by driving CS# high.  
When used to release the device from the Power-Down state and obtain the Device ID, the command is the  
same as previously described, and shown in Figure23, except that after CS# is driven high it must remain high  
for a time duration of tRES2 (See AC Characteristics). After this time duration the device will resume normal  
operation and other command will be accepted. If the Release from Power-Down/Device ID command is issued  
while an Erase, Program or Write cycle is in process (when WIP equal 1) the command is ignored and will not  
have any effects on the current cycle.  
Figure 22. Release Power-Down Sequence Diagram  
CS  
#
tRES  
1
0
1
2
3
4
5
6
7
SCLK  
SI  
Command  
ABH  
Deep Power-down mode  
Stand-by mode  
Figure 22a. Release Power-Down Sequence Diagram (QPI)  
CS#  
tRES1  
0
1
SCLK  
Command  
ABH  
IO0  
IO1  
IO2  
IO3  
Deep Power-down mode  
Stand-by mode  
Rev.1.0  
59 - 35  
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