GD25LQ40xIGx 1.8V Uniform Sector Dual and Quad Serial Flash
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7.19. Chip Erase (CE) (60/C7H)
The Chip Erase (CE) command is for erasing the all data of the chip. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit. The Chip Erase (CE) command is
entered by driving CS# Low, followed by the command code on Serial Data Input (SI). CS# must be driven Low
for the entire duration of the sequence.
The Chip Erase command sequence: CS# goes low → sending Chip Erase command → CS# goes high. The
command sequence is shown in Figure20. CS# must be driven high after the eighth bit of the command code
has been latched in, otherwise the Chip Erase command is not executed. As soon as CS# is driven high, the self-
timed Chip Erase cycle (whose duration is tCE) is initiated. While the Chip Erase cycle is in progress, the Status
Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Chip Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle
is completed, the Write Enable Latch (WEL) bit is reset. The Chip Erase (CE) command is executed only if all
Block Protect (BP4,BP3,BP2, BP1 and BP0) bits are set to “None protected”. The Chip Erase (CE) command is
ignored if one or more sectors are protected.
Figure 20. Chip Erase Sequence Diagram
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
60H or C7H
Figure 20a. Chip Erase Sequence Diagram (QPI)
CS#
0
1
SCLK
Instruction
C7H/60H
IO0
IO1
IO2
IO3
Rev.1.0
59 - 33
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