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GD25LQ40 参数 Datasheet PDF下载

GD25LQ40图片预览
型号: GD25LQ40
PDF下载: 下载PDF文件 查看货源
内容描述: [1.8V Uniform Sector Dual and Quad Serial Flash]
分类和应用:
文件页数/大小: 59 页 / 3629 K
品牌: ELM [ ELM ELECTRONICS ]
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GD25LQ40xIGx 1.8V Uniform Sector Dual and Quad Serial Flash  
http://www.elm-tech.com  
7.20. Deep Power-Down (DP) (B9H)  
Executing the Deep Power-Down (DP) command is the only way to put the device in the lowest consumption  
mode (the Deep Power-Down Mode). It can also be used as an extra software protection mechanism, while  
the device is not in active use, since in this mode, the device ignores all Write, Program and Erase commands.  
Driving CS# high deselects the device, and puts the device in the Standby Mode (if there is no internal cycle  
currently in progress). But this mode is not the Deep Power-Down Mode. The Deep Power-Down Mode can  
only be entered by executing the Deep Power-Down (DP) command. Once the device has entered the Deep  
Power-Down Mode, all commands are ignored except the Release from Deep Power-Down and Read Device  
ID (RDI) command. This releases the device from this mode. The Release from Deep Power-Down and Read  
Device ID (RDI) command also allows the Device ID of the device to be output on SO.  
The Deep Power-Down Mode automatically stops at Power-Down, and the device always Power-Up in  
the Standby Mode. The Deep Power-Down (DP) command is entered by driving CS# low, followed by the  
command code on SI. CS# must be driven low for the entire duration of the sequence.  
The Deep Power-Down command sequence: CS# goes low → sending Deep Power-Down command → CS#  
goes high. The command sequence is shown in Figure21. CS# must be driven high after the eighth bit of the  
command code has been latched in; otherwise the Deep Power-Down (DP) command is not executed. As soon  
as CS# is driven high, it requires a delay of tDP before the supply current is reduced to ICC2 and the Deep Power-  
Down Mode is entered. Any Deep Power-Down (DP) command, while an Erase, Program or Write cycle is in  
progress, is rejected without having any effects on the cycle that is in progress.  
Figure 21. Deep Power-Down Sequence Diagram  
CS#  
t
DP  
0
1 2 3 4 5 6 7  
SCLK  
SI  
Command  
B9H  
Stand-by mode Deep Power-down mode  
Figure 21a. Deep Power-Down Sequence Diagram (QPI)  
CS#  
tDP  
0
1
SCLK  
Command  
B9H  
IO0  
IO1  
IO2  
IO3  
Stand-by mode  
Deep Power-down mode  
Rev.1.0  
59 - 34  
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