DA14580
FINAL
Bluetooth Low Energy 4.2 SoC
Table 83: UART_HTX_REG (0x500010A4)
Bit
Mode Symbol
R/W UART_HALT_TX
Description
Reset
0
This register is use to halt transmissions for testing, so that
the transmit FIFO can be filled by the master when FIFOs
are implemented and enabled.
0x0
0 = Halt TX disabled
1 = Halt TX enabled
Note, if FIFOs are implemented and not enabled, the setting
of the halt TX register has no effect on operation.
Table 84: UART_CPR_REG (0x500010F4)
Bit
Mode Symbol
CPR
Description
Reset
15:0
R
Component Parameter Register
0x0
Table 85: UART_UCV_REG (0x500010F8)
Bit
Mode Symbol
UCV
Description
Reset
15:0
R
Component Version
0x33303
82A
Table 86: UART_CTR_REG (0x500010FC)
Bit
Mode Symbol
CTR
Description
Reset
15:0
R
Component Type Register
0x44570
110
Table 87: UART2_RBR_THR_DLL_REG (0x50001100)
Bit
Mode Symbol
Description
Reset
15:8
-
-
Reserved
0x0
Datasheet
Revision 3.4
09-Nov-2016
CFR0011-120-01
66 of 155
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