DA14580
FINAL
Bluetooth Low Energy 4.2 SoC
Table 43: QDEC_YCNT_REG (0x50000204)
Bit
Mode Symbol
Y_COUNTER
Description
Reset
15:0
R
Contains a signed value of the events. Zero when channel is
disabled
0x0
Table 44: QDEC_CLOCKDIV_REG (0x50000206)
Bit
Mode Symbol
R/W CLOCK_DIVIDER
Description
Reset
9:0
Contains the number of the input clock cycles minus one,
that are required to generate one logic clock cycle.
0x0
Table 45: QDEC_CTRL2_REG (0x50000208)
Bit
Mode Symbol
Description
Reset
15:12
11:8
-
-
Reserved
0
0
R/W
CHZ_PORT_SEL
Defines which GPIOs are mapped on Channel Z
0: none
1: P0[0] -> CHZ_A, P0[1] -> CHZ_B
2: P0[2] -> CHZ_A, P0[3] -> CHZ_B
3: P0[4] -> CHZ_A, P0[5] -> CHZ_B
4: P0[6] -> CHZ_A, P0[7] -> CHZ_B
5: P1[0] -> CHZ_A, P1[1] -> CHZ_B
6: P1[2] -> CHZ_A, P1[3] -> CHZ_B
7: P2[3] -> CHZ_A, P2[4] -> CHZ_B
8: P2[5] -> CHZ_A, P2[6] -> CHZ_B
9: P2[7] -> CHZ_A, P2[8] -> CHZ_B
10: P2[9] -> CHZ_A, P2[0] -> CHZ_B
11..15: None
7:4
R/W
CHY_PORT_SEL
Defines which GPIOs are mapped on Channel Y
0: none
0
1: P0[0] -> CHY_A, P0[1] -> CHY_B
2: P0[2] -> CHY_A, P0[3] -> CHY_B
3: P0[4] -> CHY_A, P0[5] -> CHY_B
4: P0[6] -> CHY_A, P0[7] -> CHY_B
5: P1[0] -> CHY_A, P1[1] -> CHY_B
6: P1[2] -> CHY_A, P1[3] -> CHY_B
7: P2[3] -> CHY_A, P2[4] -> CHY_B
8: P2[5] -> CHY_A, P2[6] -> CHY_B
9: P2[7] -> CHY_A, P2[8] -> CHY_B
10: P2[9] -> CHY_A, P2[0] -> CHY_B
11..15: None
3:0
R/W
CHX_PORT_SEL
Defines which GPIOs are mapped on Channel X
0: none
0
1: P0[0] -> CHX_A, P0[1] -> CHX_B
2: P0[2] -> CHX_A, P0[3] -> CHX_B
3: P0[4] -> CHX_A, P0[5] -> CHX_B
4: P0[6] -> CHX_A, P0[7] -> CHX_B
5: P1[0] -> CHX_A, P1[1] -> CHX_B
6: P1[2] -> CHX_A, P1[3] -> CHX_B
7: P2[3] -> CHX_A, P2[4] -> CHX_B
8: P2[5] -> CHX_A, P2[6] -> CHX_B
9: P2[7] -> CHX_A, P2[8] -> CHX_B
10: P2[9] -> CHX_A, P2[0] -> CHX_B
11..15: None
Datasheet
Revision 3.4
09-Nov-2016
CFR0011-120-01
37 of 155
© 2014 Dialog Semiconductor
DIALOG [ Dialog Semiconductor ]
