DA14580
FINAL
Bluetooth Low Energy 4.2 SoC
Table 5: Register Map
Address
Port
Description
0x40008000
0x40008004
0x40008008
0x4000800C
0x40008010
0x40008014
0x40008018
0x4000801C
0x50000000
0x50000002
0x50000004
0x50000008
0x5000000A
0x50000010
0x50000012
0x50000014
0x50000016
0x50000020
0x50000022
0x50000024
0x50000028
0x5000002A
0x50000100
0x50000102
0x50000104
0x50000106
0x50000108
0x5000010A
OTPC_MODE_REG
OTPC_PCTRL_REG
OTPC_STAT_REG
OTPC_AHBADR_REG
OTPC_CELADR_REG
OTPC_NWORDS_REG
OTPC_FFPRT_REG
OTPC_FFRD_REG
CLK_AMBA_REG
Mode register
Bit-programming control register
Status register
AHB master start address
Macrocell start address
Number of words
Ports access to fifo logic
Latest read data from the OTPC_FFPRT_REG
HCLK, PCLK, divider and clock gates
Xtal frequency trimming register
Peripheral divider register
Radio PLL control register
Clock control register
CLK_FREQ_TRIM_REG
CLK_PER_REG
CLK_RADIO_REG
CLK_CTRL_REG
PMU_CTRL_REG
Power Management Unit control register
System Control register
SYS_CTRL_REG
SYS_STAT_REG
System status register
TRIM_CTRL_REG
CLK_32K_REG
Control trimming of the XTAL16M
32 kHz oscillator register
16 MHz RC-oscillator register
20 kHz RXC-oscillator control register
Bandgap trimming
CLK_16M_REG
CLK_RCX20K_REG
BANDGAP_REG
ANA_STATUS_REG
WKUP_CTRL_REG
WKUP_COMPARE_REG
WKUP_RESET_IRQ_REG
WKUP_COUNTER_REG
WKUP_RESET_CNTR_REG
WKUP_SELECT_P0_REG
Status bit of analog (power management) circuits
Control register for the wakeup counter
Number of events before wakeup interrupt
Reset wakeup interrupt
Actual number of events of the wakeup counter
Reset the event counter
Select which inputs from P0 port can trigger wkup
counter
0x5000010C
0x5000010E
0x50000110
WKUP_SELECT_P1_REG
WKUP_SELECT_P2_REG
WKUP_SELECT_P3_REG
Select which inputs from P1 port can trigger wkup
counter
Select which inputs from P2 port can trigger wkup
counter
Select which inputs from P3 port can trigger wkup
counter
0x50000112
0x50000114
0x50000116
0x50000118
0x50000200
0x50000202
0x50000204
0x50000206
0x50000208
WKUP_POL_P0_REG
WKUP_POL_P1_REG
WKUP_POL_P2_REG
WKUP_POL_P3_REG
QDEC_CTRL_REG
Select the sensitivity polarity for each P0 input
Select the sensitivity polarity for each P1 input
Select the sensitivity polarity for each P2 input
Select the sensitivity polarity for each P3 input
Quad Decoder control register
QDEC_XCNT_REG
QDEC_YCNT_REG
QDEC_CLOCKDIV_REG
QDEC_CTRL2_REG
Counter value of the X Axis
Counter value of the Y Axis
Clock divider register
Quad Decoder control register
Datasheet
Revision 3.4
09-Nov-2016
CFR0011-120-01
19 of 155
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