DA14580
FINAL
Bluetooth Low Energy 4.2 SoC
Table 243: SET_FREEZE_REG (0x50003300)
Bit
Mode Symbol
Description
Reset
3
R/W
FRZ_WDOG
If '1', the watchdog timer is frozen, '0' is discarded.
WATCHDOG_CTRL_REG[NMI_RST] must be '0' to allow
the freeze function.
0x0
2
1
0
R/W
R/W
R/W
FRZ_BLETIM
FRZ_SWTIM
FRZ_WKUPTIM
If '1', the BLE master clock is frozen, '0' is discarded.
If '1', the SW Timer (TIMER0) is frozen, '0' is discarded.
If '1', the Wake Up Timer is frozen, '0' is discarded.
0x0
0x0
0x0
Table 244: RESET_FREEZE_REG (0x50003302)
Bit
15:4
3
Mode Symbol
Description
Reset
0x0
-
-
Reserved
R/W
R/W
R/W
R/W
FRZ_WDOG
FRZ_BLETIM
FRZ_SWTIM
FRZ_WKUPTIM
If '1', the watchdog timer continues, '0' is discarded.
If '1', the the BLE master clock continues, '0' is discarded.
If '1', the SW Timer (TIMER0) continues, '0' is discarded.
If '1', the Wake Up Timer continues, '0' is discarded.
0x0
2
0x0
1
0x0
0
0x0
Table 245: DEBUG_REG (0x50003304)
Bit
15:1
0
Mode Symbol
Description
Reset
0x0
-
-
Reserved
R/W
DEBUGS_FREEZE_
EN
Default '1', freezing of the on-chip timers is enabled when the
Cortex-M0 is halted in DEBUG State.
0x1
If '0', freezing of the on-chip timers is depending on
FREEZE_REG when the Cortex-M0 is halted in DEBUG
State except the watchdog timer. The watchdog timer is
always frozen when the Cortex-M0 is halted in DEBUG
State.
Table 246: GP_STATUS_REG (0x50003306)
Bit
15:1
0
Mode Symbol
Description
Reset
0x0
-
-
Reserved
R/W
CAL_PHASE
If '1', it designates that the chip is in Calibration Phase i.e.
the OTP has been initially programmed but no Calibration
has occured.
0x0
Table 247: GP_CONTROL_REG (0x50003308)
Bit
Mode Symbol
Description
Reset
15:6
-
-
Reserved
0
Datasheet
Revision 3.4
09-Nov-2016
CFR0011-120-01
136 of 155
© 2014 Dialog Semiconductor
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