P E R F O R M A N C E
I M P R O V E M E N T
The following table gives a survey about
the Core area and performance in the
ALTERA® devices after Place & Route:
Most instruction of DFPIC165X is executed
within 2 CLK cycles. Except the conditional
program memory branches in case that the
condition of branch instruction is met. The
table below shows sample instructions execu-
tion times:
Speed
grade
-6
Device
Logic Cells
Fmax
CYCLONE
CYCLONE II
STRATIX
STRATIX II
STRATIX GX
APEX II
APEX20KC
APEX20KE
APEX20K
ACEX1K
551
547
551
456
551
635
635
635
635
648
648
105 MHz
108 MHz
108 MHz
178 MHz
109 MHz
73 MHz
68 MHz
56 MHz
45 MHz
50 MHz
48 MHz
-6
-5
-3
-5
-7
-7
-1
-1
Mnemonic
operands
ADDWF
ANDWF
RLF
DFPIC165X
PIC16C54
Impr.
(CLK cycles)
(CLK cycles)
2
2
2
4
4
4
2
2
2
2
2
2
2
2
4
4
4
BCF
2
4
DECFSZ
INCFSZ
BTFSC
BTFSS
CALL
2(4)1
2(4)1
2(4)1
2(4)1
2
4(8)1
4(8)1
4(8)1
4(8)1
8
-1
-1
FLEX10KE
*CPU – consisted of ALU, Control Unit, Bus Controller, Hardware Stack,
256 B RAM, 4k of Program memory
Core performance in ALTERA® devices
GOTO
2
8
RETLW
2
8
1- number of clock in case that result of operation is 0.
D F P I C & D R P I C F A M I L Y O V E R V I E W
The family of DCD DFPICXX & DRPICXX IP Cores combine a high–performance, low cost, and
small compact size, offering the best price/performance ratio in the IP Market. The DCD’s Cores are
dedicated for use in cost-sensitive consumer products, computer peripherals, office automation,
automotive control systems, security and telecommunication applications.
DCD’s DFPICXX & DRPICXX IP Cores family contains four 8-bit microcontroller Cores to best
meet your needs: DFPIC165X 12-bit program word, DFPIC1655X 14-bit program word, and
DRPIC1655X and DRPIC166X single cycle microcontrollers with 14-bit program word. All three mi-
crocontroller cores are binary compatible with widely accepted PIC16C5X and PIC16CXXX. They
employ a modified RISC architecture two or four times faster than the original ones.
The DFPICXXX & DRPICXX IP Cores are written in pure VHDL/VERILOG HDL languages which
make them technologically independent. All of the DFPICXX & DRPICXX family members supports a
power saving SLEEP mode and allows the user to configure the watchdog time-out period and a
number of hardware stack levels. DFPICXX & DRPICXX can be fully customized according to cus-
tomer needs.
Design
DFPIC165X
DFPIC1655X
DRPIC1655X
DRPIC166X
2k 128 12 33 24
64k 512 14 35 16
64k 512 14 35 32
64k 512 14 35 32
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2
8
8
8
-
2
2
4
4
-
2 700
3 900
4 800
6 700
5
5
5
1
1
5
*
*
*
* Optional
DFPIC & DRPIC family of High Performance Microcontroller Cores
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
DCD [ DIGITAL CORE DESIGN ]
